Xilinx 7 Series User Manual page 27

X-Ref Target - Figure 2-3
Ports and Attributes
Table 2-4
primitive.
Table 2-4: GTPE2_COMMON Clocking Ports
GTGREFCLK0
GTGREFCLK1
GTREFCLK0
GTREFCLK1
GTWESTREFCLK0
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
PLL0REFCLKSEL[2:0]
GTREFCLK0
GTREFCLK1
GTEASTREFCLK0
GTEASTREFCLK1
GTWESTREFCLK0
GTWESTREFCLK1
GTGREFCLK0
PLL1REFCLKSEL[2:0]
GTGREFCLK1
Figure 2-3: PLL0 and PLL1 Reference Clock Selection Multiplexer
and Table 2-5 define the clocking ports and attributes for the GTPE2_COMMON
Port Direction
In
In
In
In
In
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Reference Clock Selection and Distribution
GTPE2_COMMON
0
1
2
3
PLL0
4
5
6
7
0
1
2
3
PLL1
4
5
6
7
Clock
Domain
Clock Reference clock generated by the internal
FPGA logic. This input is reserved for internal
testing purposes only.
Clock Reference clock generated by the internal
FPGA logic. This input is reserved for internal
testing purposes only.
Clock External clock driven by IBUFDS_GTE2 for
PLL0 and/or PLL1.
Clock External clock driven by IBUFDS_GTE2 for
PLL0 and/or PLL1.
Clock West-bound clock from the Quad on the right
side of the device.
PLL0 Output CLK
PLL1 Output CLK
UG482_c2_03_112811
Description
27
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