Xilinx 7 Series User Manual page 179

X-Ref Target - Figure 4-36
Figure 4-37
alignment to adjust RXUSRCLK to compensate for temperature and voltage variations.
X-Ref Target - Figure 4-37
RXDLYSRESET
RXDLYSRESETDONE
RXPHALIGNDONE
RXSYNCDONE
Figure 4-37: RX Buffer Bypass Example—Single-Lane Auto Mode
Notes relevant to
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6.
It is necessary to start the RX phase alignment after RX CDR is locked to ensure that the RX
recovered clock and RXUSRCLK are stable and ready to be used for alignment. When the RX
elastic buffer is bypassed, data received from the PMA can be distorted due to phase differences
after conditions such as a GTP transceiver reset or rate change. If the received data evaluated at the
fabric interface is invalid, the RX phase alignment needs to be repeated while the RX CDR is
locked.
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
RXSYNCALLIN
RXSYNCIN
1'b0
RXSYNCMODE
1'b1
RXDLYSRESET
Figure 4-36: RX Buffer Bypass—Single-Lane, Auto Mode Port Connection
shows the required steps to perform the auto RX phase alignment and use the RX delay
Figure 4-37:
The sequence of events in Figure 4-37
After conditions such as a GTP receiver reset or RX rate change, RX phase alignment must be
performed to align XCLK and RXUSRCLK. Wait until exiting RXELECIDLE and RX CDR is
locked before asserting RXDLYSRESET to start the RX phase and delay alignments. The
assertion of RXDLYSRESET should be less than 50 ns.
Wait until RXDLYSRESETDONE is High. RXDLYSRESETDONE will stay asserted for a
minimum of 100 ns.
When RXSYNCDONE is asserted, the alignment procedure is completed. This signal will
remain asserted until the alignment procedure is re-initiated.
Upon the assertion of RXSYNCDONE, RXPHALIGNDONE indicates whether alignment is
achieved and maintained.
RX delay alignment continues to adjust RXUSRCLK to compensate for temperature and
voltage variations.
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RXPHALIGNDONE
RXSYNCOUT
RXSYNCDONE
is not drawn to scale.
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RX Buffer Bypass
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