Xilinx 7 Series User Manual page 304

Appendix D: DRP Address Map of the GTP Transceiver
Table D-2: DRP Map of GTPE2_CHANNEL Primitive (Cont'd)
DRP
DRP Bits
Address
6:1
009D
304
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R/W Attribute Name
R/W RXBUF_THRESH_OVFLW
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Attribute Attribute
Bits Encoding
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
5:0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
DRP
Encoding
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31