Xilinx 7 Series User Manual page 295

Table D-2: DRP Map of GTPE2_CHANNEL Primitive (Cont'd)
DRP
DRP Bits
Address
0047
14:10
(Cont'd)
9:0
0047
14
0048
13:10
0048
9:0
0048
14
0049
12
0049
11:10
0049
9:0
0049
9:0
004A
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
R/W Attribute Name
R/W CLK_COR_REPEAT_WAIT
R/W CLK_COR_SEQ_1_4
R/W CLK_COR_SEQ_2_USE
R/W CLK_COR_SEQ_2_ENABLE
R/W CLK_COR_SEQ_2_1
R/W CLK_COR_KEEP_IDLE
R/W CLK_COR_PRECEDENCE
R/W CLK_COR_SEQ_LEN
R/W CLK_COR_SEQ_2_2
R/W CLK_COR_SEQ_2_3
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Attribute Attribute
Bits Encoding
15
16
17
18
19
20
21
22
4:0 23
24
25
26
27
28
29
30
31
9:0 0-1023
FALSE
0
TRUE
3:0 0-15
9:0 0-1023
FALSE
0
TRUE
FALSE
0
TRUE
1
2
1:0
3
4
9:0 0-1023
9:0 0-1023
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DRP
Encoding
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0-1023
0
1
0-15
0-1023
0
1
0
1
0
1
2
3
0-1023
0-1023
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