Xilinx 7 Series User Manual page 305

Table D-2: DRP Map of GTPE2_CHANNEL Primitive (Cont'd)
DRP
DRP Bits
Address
009D
6:1
(Cont'd)
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
R/W Attribute Name
R/W RXBUF_THRESH_OVFLW
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Attribute Attribute
Bits Encoding
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
5:0
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
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DRP
Encoding
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
305