Xilinx 7 Series User Manual page 71

Ports and Attributes
Table 2-31
Table 2-31: Digital Monitor Ports
DMONITOROUT[14:0]
DMONITORCLK
DMONFIFORESET
Table 2-32
Table 2-32: Digital Monitor Attributes
RX_DEBUG_CFG[13:0]
CFOK_CFG[42]
DMONITOR_CFG[23:0]
Table 2-33: Select Adaptation Loop Description Details
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
shows the digital monitor ports.
Port
shows the digital monitor attributes.
Attribute
DRP Address DRP DI
0x0A5 0x00C2
0x0A5 0x00C3
0x0A5 0x00C4
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Dir Clock Domain
Out Async/Local Clock
In Async
In DMONITORCLK
Type
14-bit [13:8] - Reserved. Set to 6'h00
Binary
[7:6] - Reserved. Set to 2'b11.
[5] - Reserved. Set to 1'b0.
[4:0] - Select adaptation loop: See
1-bit Reserved. Set to 1'b1.
Binary
24-bit Reserved. Set to 24'h008101.
Binary
Loop Description
RXLPMOS -Base line wander cancellation
7-bit signed with double neutral
RXLPMHF - LPM high-frequency gain
RXLPMLF - LPM low-frequency gain
Digital Monitor
Description
Digital Monitor Output Bus:
• [14:8] Unused
• [7] - Internal Clock
Adaptation loops:
• [6:0] RXOS
• [6:3] RXLPMHF, RXLPMLF
Digital monitor clock
Reserved. Tie To GND. Reset use
for sync mode operation.
Description
Table 2-33.
Code Mapping
7'd0 - min (neg)
7'63 - neutral
7'64 - neutral
7'127 - max (pos)
4'd0 - min
4'd15 - max
4'd0 - min
4'd15 - max
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