Xilinx 7 Series User Manual page 32

Chapter 2: Shared Features
X-Ref Target - Figure 2-4
IBUFDS_GTE2
GTREFCLK0
IBUFDS_GTE2
GTREFCLK1
Single External Reference Clock Use Model
In the single external reference clock use model, the user connects the IBUFDS_GTE2 output (O) to
the GTREFCLK0 input port of the GTPE2_COMMON primitive. The user design can leave the
other unused reference clock ports floating. The IBUFDS_GTE2 input pins can be constrained in
the user constraints file (UCF).
to a single IBUFDS_GTE2 primitive.
X-Ref Target - Figure 2-5
32
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GTPE2_COMMON
PLL0OUTCLK
PLL0
PLL0OUTREFCLK
PLL1OUTCLK
PLL1
PLL1OUTREFCLK
Figure 2-4: External Reference Clock Use Case
Figure 2-5
GTP Quad
GTPE2_
CHANNEL
GTREFCLK0
IBUFDS_GTE2
Figure 2-5: Single GTP Quad with a Single Local Reference Clock
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TXSYSCLKSEL[0]
PLL0CLK
PLL1CLK
RXSYSCLKSEL[0]
TXSYSCLKSEL[1]
PLL0REFCLK
PLL1REFCLK
RXSYSCLKSEL[1]
shows a single GTPE2_COMMON primitive connected
GTPE2_ GTPE2_ GTPE2_
CHANNEL CHANNEL CHANNEL
GTPE2_COMMON
UG482_c2_05_110811
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
GTPE2_CHANNEL
0
TX
1
0
RX
1
TXOUTCLKSEL
0
TXOUTCLK
1
0
RXOUTCLK
1
RXOUTCLKSEL
UG482_c2_04_110811