Chapter 2: Shared Transceiver Features; Reference Clock Input Structure; Functional Description; Ports And Attributes - Xilinx Virtex-6 FPGA User Manual

Shared Transceiver Features

Reference Clock Input Structure

Functional Description

The reference clock input structure is illustrated in
internally with 50 on each leg to 4/5MGTAVCC. The reference clock is instantiated in
software with the IBUFDS_GTXE1 software primitive. The ports and attributes controlling
the reference clock input are tied to the IBUFDS_GTXE1 software primitive.
X-Ref Target - Figure 2-1
MGTAVCC = 1.0V
MGTAVSS
I
MGTREFCLKP0/1
MGTREFCLKN0/1
IB

Ports and Attributes

Table 2-1
Table 2-1: Reference Clock Input Ports (IBUFDS_GTXE1)
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Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Nom
50Ω
CLKRCV_TRST =
Nom
50Ω
Figure 2-1: Reference Clock Input Structure
defines the reference clock input ports in the IBUFDS_GTXE1 software primitive.
Port Dir Clock Domain
I In
IB (Pad)
CEB In
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Figure
CLKCM_CFG
+
4/5 MGTAVCC
–
N/A These are the reference clock input ports that get
mapped to MGTREFCLK0P/MGTREFCLK0N and
MGTREFCLK1P/MGTREFCLK1P.
N/A This is the active-Low asynchronous clock enable
signal for the clock buffer. Pulling this signal High
powers down the clock buffer.
Chapter 2
2-1. The input is terminated
O
/2 ODIV2
UG366_c2_10_110210
Description
101