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Xilinx RocketIO User Manual

Xilinx RocketIO User Manual

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RocketIO™
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UG024 (v2.3.2) June 24, 2004
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  • Page 1: User Guide

    RocketIO™ Transceiver User Guide UG024 (v2.3.2) June 24, 2004...
  • Page 2 Xilinx, Inc. assumes no obligation to correct any errors contained herein or to advise any user of this text of any correction if such be made. Xilinx, Inc. will not assume any liability for the accuracy or correctness of any engineering or software support or assistance provided to a user.
  • Page 3 02/25/02 • Updated 07/11/02 “PCB Design Requirements”. Added Appendix A, “RocketIO Transceiver Timing Model.” Changed Cell Models to Appendix B. • Added additional IMPORTANT NOTE regarding ISE revisions at the beginning of Chapter 1 09/27/02 • Added material in section “CRC (Cyclic Redundancy Check).”...
  • Page 4 1-2: Added qualifying footnote to XAUI 10GFC. • Table 1-5: Corrected definition of RXRECCLK. • Section “RocketIO Transceiver Instantiations” in Chapter 1: added text briefly explaining what the Instantiation Wizard does. • Table 2-14: Changed numerics from exact values to rounded-off approximations (nearest 5,000), and added footnote calling attention to this.
  • Page 5 3: Added Linear Technology part numbers (LT1963A, LT1964). • Section “Passive Filtering” in Chapter 3: Added new cap rules for RocketIO transceiver. • Figure 3-8, page 109: Replaced old Figure 3-8 with new figure showing “Power Filtering Network on Devices with Internal and External Capacitors.”...
  • Page 6 RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v2.3.2) June 24, 2004 1-800-255-7778...

  • Page 7: Table Of Contents

    Online Document ............20 Chapter 1: RocketIO Transceiver Overview Basic Architecture and Capabilities .
  • Page 8 Overview ..............76 www.xilinx.com RocketIO™ Transceiver User Guide 1-800-255-7778...
  • Page 9 RocketIO CRC Support Limitations ........
  • Page 10 Powering the RocketIO Transceivers ........
  • Page 11 Differential Swing Control Attributes ........144 XAPP661: RocketIO Transceiver Bit-Error Rate Tester ......144 XAPP662: In-Circuit Partial Reconfiguration of RocketIO Attributes .
  • Page 12 RocketIO™ Transceiver User Guide 1-800-255-7778 UG024 (v2.3.2) June 24, 2004...

  • Page 13: Schedule Of Figures

    Figure 1-1: RocketIO Transceiver Block Diagram ........
  • Page 14 Figure A-1: RocketIO Transceiver Block Diagram ....... . . 126...

  • Page 15: Schedule Of Tables

    Chapter 1: RocketIO Transceiver Overview Table 1-1: Number of RocketIO Cores per Device Type......21 Table 1-2: Communications Standards Supported by RocketIO Transceiver .
  • Page 16 Table A-1: RocketIO Clock Descriptions ........

  • Page 17: Preface: About This Guide

    Preface About This Guide The RocketIO Transceiver User Guide provides the product designer with the detailed technical information needed to successfully implement the RocketIO™ multi-gigabit transceiver in Virtex-II Pro Platform FPGA designs. RocketIO Features The RocketIO transceiver’s flexible, programmable features allow a multi-gigabit serial transceiver to be easily integrated into any Virtex-II Pro design: •...

  • Page 18: For More Information

    Appendix C, “Related Online Documents” — Bibliography of online Application Notes, Characterization Reports, and White Papers. For More Information For a complete menu of online information resources available on the Xilinx website, visit http://www.xilinx.com/virtex2pro/ or refer to Appendix C, “Related Online Documents.”...

  • Page 19: Conventions

    Port and Attribute Names Input and output ports of the RocketIO transceiver primitives are denoted in upper-case letters. Attributes of the RocketIO transceiver are denoted in upper-case letters with underscores. Trailing numbers in primitive names denote the byte width of the data path. These values are preset and not modifiable.

  • Page 20: Online Document

    Cross-reference link to a location Figure 2-5 in the Virtex-II Red text in another document Handbook. Go to http://www.xilinx.com Blue, underlined text Hyperlink to a website (URL) the latest speed files. www.xilinx.com RocketIO™ Transceiver User Guide 1-800-255-7778 UG024 (v2.3.2) June 24, 2004...

  • Page 21: Basic Architecture And Capabilities

    Chapter 1 RocketIO Transceiver Overview Basic Architecture and Capabilities The RocketIO transceiver is based on Mindspeed’s SkyRail™ technology. Figure 1-1, page depicts an overall block diagram of the transceiver. Up to 20 transceiver modules are available on a single Virtex-II Pro FPGA, depending on the part being used.
  • Page 22 LOOPBACK[1:0] TXRESET RXRESET REFCLK REFCLK2 GNDA TX/RX GND REFCLKSEL BREFCLK AVCCAUXTX 2.5V TX BREFCLK2 RXUSRCLK VTTX Termination Supply TX RXUSRCLK2 TXUSRCLK TXUSRCLK2 DS083-2_04_090402 Figure 1-1: RocketIO Transceiver Block Diagram www.xilinx.com RocketIO™ Transceiver User Guide 1-800-255-7778 UG024 (v2.3.2) June 24, 2004...

  • Page 23: Rocketio Transceiver Instantiations

    • Dynamic changes can be made by the ports of the primitives The RocketIO transceiver consists of the Physical Media Attachment (PMA) and Physical Coding Sublayer (PCS). The PMA contains the serializer/deserializer (SERDES), TX and RX buffers, clock generator, and clock recovery circuitry. The PCS contains the 8B/10B encoder/decoder and the elastic buffer supporting channel bonding and clock correction.

  • Page 24: List Of Available Ports

    Chapter 1: RocketIO Transceiver Overview List of Available Ports The RocketIO transceiver primitives contain 50 ports, with the exception of the 46-port GT_ETHERNET and GT_FIBRE_CHAN primitives. The differential serial data ports (RXN, RXP, TXN, and TXP) are connected directly to external pads; the remaining 46 ports are all accessible from the FPGA logic (42 ports for GT_ETHERNET and GT_FIBRE_CHAN).
  • Page 25 Bit 0 = Resync state (High) If RX_LOSS_OF_SYNC_FSM = FALSE, RXLOSSOFSYNC indicates: Bit 1 = Received data invalid (High) Bit 0 = Channel bonding sequence recognized (High) Serial differential port (FPGA external) RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v2.3.2) June 24, 2004 1-800-255-7778...
  • Page 26 Chapter 1: RocketIO Transceiver Overview Table 1-5: GT_CUSTOM , GT_AURORA, GT_FIBRE_CHAN , GT_ETHERNET GT_INFINIBAND, and GT_XAUI Primitive Ports (Continued) Port Port Definition Size RXNOTINTABLE 1, 2, 4 Status of encoded data when the data is not a valid character when asserted High.
  • Page 27 2. GT_FIBRE_CHAN and GT_ETHERNET ports do not have the three CHBOND** or ENCHANSYNC ports. 3. The port size changes with relation to the primitive selected, and also correlates to the byte mapping. 4. External ports only accessible from package pins. RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v2.3.2) June 24, 2004...

  • Page 28: Primitive Attributes

    Chapter 1: RocketIO Transceiver Overview Primitive Attributes The primitives also contain attributes set by default to specific values controlling each specific primitive’s protocol parameters. Included are channel-bonding settings (for primitives supporting channel bonding), clock correction sequences, and CRC. Table 1-6 shows a brief description of each attribute.
  • Page 29 Primitive Attributes Table 1-6: RocketIO Transceiver Attributes (Continued) Attribute Description CHAN_BOND_OFFSET Integer 0-15 that defines offset (in bytes) from channel bonding sequence for realignment. It specifies the first elastic buffer read address that all channel-bonded transceivers have immediately after channel bonding.
  • Page 30 Chapter 1: RocketIO Transceiver Overview Table 1-6: RocketIO Transceiver Attributes (Continued) Attribute Description CLK_COR_INSERT_IDLE_FLAG TRUE/FALSE controls whether RXRUNDISP input status denotes running disparity or inserted-idle flag. FALSE: RXRUNDISP denotes running disparity when RXDATA is decoded data. TRUE: RXRUNDISP is raised for the first byte of each inserted (repeated) clock correction (“Idle”) sequence (when RXDATA is decoded data).
  • Page 31 Primitive Attributes Table 1-6: RocketIO Transceiver Attributes (Continued) Attribute Description CRC_FORMAT ETHERNET, INFINIBAND, FIBRE_CHAN, USER_MODE CRC algorithm selection. Modifiable only for GT_AURORA_n, GT_XAUI_n, and GT_CUSTOM. USER_MODE allows user definition of Start of Packet (SOP) and End of Packet (EOP) K-characters.
  • Page 32 Chapter 1: RocketIO Transceiver Overview Table 1-6: RocketIO Transceiver Attributes (Continued) Attribute Description RX_DECODE_USE This determines if the 8B/10B decoding is bypassed. FALSE denotes that it is bypassed. RX_LOS_INVALID_INCR Power of two in a range of 1 to 128 that denotes the number of valid characters required to “cancel out”...

  • Page 33: Modifiable Primitives

    CLK_COR_KEEP_IDLE FALSE FALSE FALSE CLK_COR_REPEAT_WAIT CLK_COR_SEQ_1_1 00111110111 00000000000 00110111100 CLK_COR_SEQ_1_2 00111110111 00000000000 00001010000 CLK_COR_SEQ_1_3 00111110111 00000000000 00000000000 CLK_COR_SEQ_1_4 00111110111 00000000000 00000000000 CLK_COR_SEQ_2_1 00000000000 00000000000 00000000000 CLK_COR_SEQ_2_2 00000000000 00000000000 00000000000 RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v2.3.2) June 24, 2004 1-800-255-7778...
  • Page 34 Chapter 1: RocketIO Transceiver Overview Table 1-7: Default Attribute Values: GT_AURORA, GT_CUSTOM, GT_ETHERNET (Continued) Default Default Default Attribute GT_AURORA GT_CUSTOM GT_ETHERNET CLK_COR_SEQ_2_3 00000000000 00000000000 00000000000 CLK_COR_SEQ_2_4 00000000000 00000000000 00000000000 CLK_COR_SEQ_2_USE FALSE FALSE FALSE CLK_COR_SEQ_LEN CLK_CORRECT_USE TRUE TRUE TRUE COMMA_10B_MASK 1111111111...
  • Page 35 Lane ID (Modify with 00000000000 00000000000 Lane ID) CHAN_BOND_SEQ_2_3 00000000000 00001000101 00000000000 CHAN_BOND_SEQ_2_4 00000000000 00001000101 00000000000 CHAN_BOND_SEQ_2_USE FALSE TRUE FALSE CHAN_BOND_SEQ_LEN CHAN_BOND_WAIT CLK_COR_INSERT_IDLE_FLAG FALSE FALSE FALSE CLK_COR_KEEP_IDLE FALSE FALSE FALSE RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v2.3.2) June 24, 2004 1-800-255-7778...
  • Page 36 Chapter 1: RocketIO Transceiver Overview Table 1-8: Default Attribute Values: GT_FIBRE_CHAN, GT_INFINIBAND, and GT_XAUI (Continued) Default Default Default Attribute GT_FIBRE_CHAN GT_INFINIBAND GT_XAUI CLK_COR_REPEAT_WAIT CLK_COR_SEQ_1_1 00110111100 00100011100 00100011100 CLK_COR_SEQ_1_2 00010010101 00000000000 00000000000 CLK_COR_SEQ_1_3 00010110101 00000000000 00000000000 CLK_COR_SEQ_1_4 00010110101 00000000000 00000000000 CLK_COR_SEQ_2_1...

  • Page 37: Byte Mapping

    1-bit control and status bits (TXKERR[0]) correlating to the data bits TXDATA[7:0]. Footnote Table 1-5 shows the ports that use byte mapping. Table 1-9: Control/Status Bus Association to Data Bus Byte Paths Control/Status Bit Data Bits [7:0] [15:8] [23:16] [31:24] RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v2.3.2) June 24, 2004 1-800-255-7778...
  • Page 38 Chapter 1: RocketIO Transceiver Overview www.xilinx.com RocketIO™ Transceiver User Guide 1-800-255-7778 UG024 (v2.3.2) June 24, 2004...

  • Page 39: Chapter 2: Digital Design Considerations

    The reference clocks connect to the REFCLK or BREFCLK ports of the RocketIO multi-gigabit transceiver (MGT). While only one of these reference clocks is needed to drive the MGT, BREFCLK or BREFCLK2 must be used for serial speeds of 2.5 Gb/s or greater.
  • Page 40 Through BUFG? √ √ √ REFCLK √ √ BREFCLK Note (1) Note (1) Notes: 1. Because of dedicated routing to reduce jitter, BREFCLK cannot be routed through the fabric. www.xilinx.com RocketIO™ Transceiver User Guide 1-800-255-7778 UG024 (v2.3.2) June 24, 2004...

  • Page 41: Brefclk

    BREFCLK At speeds of 2.5 Gb/s or greater, REFCLK configuration introduces more than the maximum allowable jitter to the RocketIO transceiver. For these higher speeds, BREFCLK configuration is required. The BREFCLK configuration uses dedicated routing resources that reduce jitter. BREFCLK must enter the FPGA through dedicated clock I/O. BREFCLK can connect to the BREFCLK inputs of the transceiver and the CLKIN input of the DCM for creation of USRCLKs.
  • Page 42 Pin Number Pin Number Pin Number Pin Number FF896 F16/G16 G15/F15 AH16/AJ16 AJ15/AH15 FF1152 H18/J18 J17/H17 AK18/AL18 AL17/AK17 FF1148 FF1517 E20/D20 J20/K20 AR20/AT20 AL20/AK20 FF1704 G22/F22 F21/G21 AU22/AT22 AT21/AU21 FF1696 www.xilinx.com RocketIO™ Transceiver User Guide 1-800-255-7778 UG024 (v2.3.2) June 24, 2004...

  • Page 43: Clock Ratio

    1. Since CLK0 is needed for feedback, it can be used instead of CLK180 to clock USRCLK or USRCLK2 of the transceiver with the use of the transceiver’s local inverter, saving a global buffer (BUFG). RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v2.3.2) June 24, 2004...

  • Page 44: Example 1A: Two-Byte Clock With Dcm

    TWO_BYTE_CLK_arch of TWO_BYTE_CLK is -- Components Declarations: component BUFG port ( I : in std_logic; O : out std_logic end component; component IBUFG port ( I : in std_logic; www.xilinx.com RocketIO™ Transceiver User Guide 1-800-255-7778 UG024 (v2.3.2) June 24, 2004...
  • Page 45 PSINCDEC => GND, PSEN => GND, PSCLK => GND, => RST, CLK0 => CLK0_W, LOCKED => LOCK -- BUFG Instantiation U_BUFG: IBUFG port map ( => REFCLKIN, => REFCLK RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v2.3.2) June 24, 2004 1-800-255-7778...
  • Page 46 .CLK270 ( ), .CLK2X ( ), .CLK2X180 ( ), .CLKDV ( ), .CLKFX ( ), .CLKFX180 ( ), .LOCKED ( DCM_LOCKED ), .PSDONE ( ), .STATUS BUFG buf1 ( www.xilinx.com RocketIO™ Transceiver User Guide 1-800-255-7778 UG024 (v2.3.2) June 24, 2004...

  • Page 47: Example 1B: Two-Byte Clock Without Dcm

    CLKFB RXUSRCLK TXUSRCLK TXUSRCLK2 RXUSRCLK CLK0 RXUSRCLK2 MGT clock input invert- BUFG ers (acceptable skew) UG024_03_112202 Figure 2-4: Four-Byte Clock VHDL Template -- Module: FOUR_BYTE_CLK -- Description: VHDL submodule RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v2.3.2) June 24, 2004 1-800-255-7778...
  • Page 48 : out std_logic; CLK270 : out std_logic; CLK2X : out std_logic; CLK2X180 : out std_logic; CLKDV : out std_logic; CLKFX : out std_logic; CLKFX180 : out std_logic; LOCKED : out std_logic; www.xilinx.com RocketIO™ Transceiver User Guide 1-800-255-7778 UG024 (v2.3.2) June 24, 2004...
  • Page 49 O => USRCLK_M U3_BUFG: BUFG port map ( I => CLKDV_W, O => USRCLK2_M_W end FOUR_BYTE_CLK_arch; Verilog Template // Module: FOUR_BYTE_CLK // Description: Verilog Submodule DCM for 4-byte GT RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v2.3.2) June 24, 2004 1-800-255-7778...
  • Page 50 .STATUS BUFG buf1 ( .I ( clkdv2 ), .O ( USRCLK2_M ) BUFG buf2 ( .I ( clk_i ), .O ( USRCLK_M ) IBUFG buf3( .I ( REFCLKIN ), www.xilinx.com RocketIO™ Transceiver User Guide 1-800-255-7778 UG024 (v2.3.2) June 24, 2004...

  • Page 51: Example 3: One-Byte Clock

    : out std_logic; REFCLK : out std_logic; LOCK : out std_logic end ONE_BYTE_CLK; architecture ONE_BYTE_CLK_arch of ONE_BYTE_CLK is -- Components Declarations: component BUFG port ( : in std_logic; : out std_logic RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v2.3.2) June 24, 2004 1-800-255-7778...
  • Page 52 <= USRCLK_M_W; -- DCM Instantiation U_DCM: DCM port map ( CLKIN => REFCLK, CLKFB => USRCLK_M, DSSEN => GND, PSINCDEC => GND, PSEN => GND, PSCLK => GND, => RST, www.xilinx.com RocketIO™ Transceiver User Guide 1-800-255-7778 UG024 (v2.3.2) June 24, 2004...
  • Page 53 USRCLK2_M; output DCM_LOCKED; wire REFCLKIN; wire REFCLK; wire USRCLK_M; wire USRCLK2_M; wire DCM_LOCKED; wire REFCLKINBUF; wire clk_i; wire clk_2x_180; DCM dcm1 ( .CLKFB ( USRCLK_M ), .CLKIN ( REFCLKINBUF), RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v2.3.2) June 24, 2004 1-800-255-7778...
  • Page 54 .I ( clk2x_180 ), .O ( USRCLK2_M ) BUFG buf2 ( .I ( clk_i ), .O ( USRCLK_M ) IBUFGbuf3 ( .I ( REFCLKIN ), .O ( REFCLKINBUF ) endmodule www.xilinx.com RocketIO™ Transceiver User Guide 1-800-255-7778 UG024 (v2.3.2) June 24, 2004...

  • Page 55: Half-Rate Clocking Scheme

    REFCLK_P REFCLK TXUSRCLK CLKIN CLK_FX180 REFCLK_N RXUSRCLK BUFG TXUSRCLK2 TXUSRCLK RXUSRCLK2 CLKDV RXUSRCLK BUFG TXUSRCLK2 CLK0 CLKFB RXUSRCLK2 BUFG UG024_31_013103 Figure 2-8: Four-Byte Data Path Clocks, SERDES_10B = TRUE RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v2.3.2) June 24, 2004 1-800-255-7778...

  • Page 56: Multiplexed Clocking Scheme With Dcm

    DCMs. The clocks are then multiplexed before input into the RocketIO transceiver. User logic can be designed to determine during auto negotiation if the reference clock used for the transceiver is incorrect.

  • Page 57: Rxrecclk

    Module 3 of the Virtex-II Pro data sheet. The timing relationships are further discussed and illustrated in Appendix A, “RocketIO Transceiver Timing Model.” Data Path Latency With the many configurations of the MGT, the both transmit and receive data path latencies vary.

  • Page 58: Reset/Power Down

    VTTX. If VTTX is not powered, TXP/TXN float to a high-impedance state. Receive input pins RXP/RXN respond similarly to the state of receive termination supply VTRX. www.xilinx.com RocketIO™ Transceiver User Guide 1-800-255-7778 UG024 (v2.3.2) June 24, 2004...
  • Page 59 (USRCLK2_M' event and USRCLK2_M = '1') then if(DCM_LOCKED = '0') then RST <= '1'; elsif (startup_count = "00000010") then RST <= '0'; end if; RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v2.3.2) June 24, 2004 1-800-255-7778...
  • Page 60 <= startup_counter + 1; always @ ( posedge USRCLK2_M or negedge DCM_LOCKED ) if ( !DCM_LOCKED ) RST <= 1'b1; else RST <= ( startup_counter != 8'h02 ); endmodule www.xilinx.com RocketIO™ Transceiver User Guide 1-800-255-7778 UG024 (v2.3.2) June 24, 2004...

  • Page 61: 8B/10B Encoding/Decoding

    8B/10B Encoding/Decoding 8B/10B Encoding/Decoding Overview The RocketIO transceiver has the ability to encode eight bits into a 10-bit serial stream using standard 8B/10B encoding. This guarantees a DC-balanced, edge-rich serial stream, facilitating DC- or AC-coupling and clock recovery. Table 2-10, page 63, shows the significance of 8B/10B ports that change purpose, depending on whether 8B/10B is bypassed or enabled.

  • Page 62: Ports And Attributes

    Channel Bonding 20X Multiplier Clock Correction Receiver RX Clock Recovery 32/16/8 bits Deserializer Elastic 8B/10B Receive RXDATA Buffer Decode Buffer Comma Detect RX− UG024_09_031203 Figure 2-12: 8B/10B Data Flow www.xilinx.com RocketIO™ Transceiver User Guide 1-800-255-7778 UG024 (v2.3.2) June 24, 2004...

  • Page 63: Txchardispval, Txchardispmode

    TXCHARDISPVAL and TXCHARDISPMODE ports. When TXCHARDISPMODE is set High, the running disparity is set before encoding the specific byte. TXCHARDISPVAL determines if the disparity is negative (set Low) or positive (set High). Table 2-11 illustrates this. RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v2.3.2) June 24, 2004 1-800-255-7778...

  • Page 64: Txcharisk

    If a bit is asserted High, it means that TXDATA and TXCHARISK have combined to create an invalid control (K) character. The transmission, reception, and decode of this invalid character will create unexpected RXDATA results in the RocketIO receiver, or in other transceivers.

  • Page 65: Rxdisperr

    K28.5- (or K28.5+) 0 1 0 1 10111100 K28.5- (or K28.5+) The RocketIO core receives this data, but for cases where TXCHARDISPVAL is set High during data transmission, the disp_err bit in CHAN_BOND_SEQ must also be set High. RocketIO™ Transceiver User Guide www.xilinx.com...

  • Page 66: Receiving Vitesse Channel Bonding Sequence

    RX data map during 8B/10B bypass. RXCHARISK[0] RXRUNDISP[0] RXDATA[7] ..RXDATA[0] First received Last received UG024_10b_051602 Figure 2-14: 10-Bit RX Data Map with 8B/10B Bypassed www.xilinx.com RocketIO™ Transceiver User Guide 1-800-255-7778 UG024 (v2.3.2) June 24, 2004...

  • Page 67: 8B/10B Serial Output Format

    TXCHARDISPMODE, TXCHARDISPVAL, RXCHARISK, and RXRUNDISP are added to the 8- bit data bus. Please use the Architecture Wizard to create instantiation templates. This wizard creates code and instantiation templates that define the attributes for a specific application. RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v2.3.2) June 24, 2004 1-800-255-7778...

  • Page 68: Serdes Alignment

    Deserializer The RocketIO transceiver core accepts serial differential data on its RXP and RXN inputs. The clock/data recovery circuit extracts clock phase and frequency from the incoming data stream and re-times incoming data to this clock.

  • Page 69: Enpcommaalign

    For GT_X0Y0 (bottom edge), the best slices are SLICE_X14Y0 and SLICE_X14Y1. This must be done for each MGT. Figure 2-17 shows this recommendation. GT_std_ PCOMMA_CONTROL ENPCOMMAALIGN RXRECCLK MCOMMA_CONTROL ENMCOMMAALIGN UG024_39_013103 Figure 2-17: Synchronizing Comma Align Signals to RXRECCLK RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v2.3.2) June 24, 2004 1-800-255-7778...
  • Page 70 Figure 2-18: Top MGT Comma Control Flip-Flop Ideal Locations ug024_44_031303 Figure 2-19: Bottom MGT Comma Control Flip-Flop Ideal Locations www.xilinx.com RocketIO™ Transceiver User Guide 1-800-255-7778 UG024 (v2.3.2) June 24, 2004...

  • Page 71: Pcomma_Detect

    PCOMMA_10B_VALUE, MCOMMA_10B_VALUE The RocketIO transceiver allows the user to define a comma character using these three attributes. The COMMA_10B_MASK bits are used in conjunction with PCOMMA_10B_VALUE (to define a plus-comma) or MCOMMA_10B_VALUE (to define a minus-comma) to define some number of recognized comma characters.

  • Page 72: Dec_Pcomma_Detect

    The clock/data recovery (CDR) circuits lock to the reference clock automatically if the data is not present. For proper operation, TXUSRCLK must have the exact same frequency as REFCLK. www.xilinx.com RocketIO™ Transceiver User Guide 1-800-255-7778 UG024 (v2.3.2) June 24, 2004...

  • Page 73: Clock Correction

    2-20, where the solid read pointer increments to the value represented by the dashed pointer. This accelerates the emptying of the buffer, preventing its overflow. The transceiver design skips a single byte sequence, when necessary, to partially empty a buffer. If attribute RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v2.3.2) June 24, 2004...

  • Page 74: Ports And Attributes

    (See “Channel Bonding (Channel Alignment),” page 79.) It is recommended that this attribute always be set to TRUE, since this www.xilinx.com RocketIO™ Transceiver User Guide 1-800-255-7778 UG024 (v2.3.2) June 24, 2004...

  • Page 75: Clk_Cor_Seq_

    1_1, 1_2, 1_3. 1_4 2_1, 2_2, 2_3, 2_4 Notes: 1. Applicable only if CLK_COR_SEQ_2_USE is set to TRUE. CLK_COR_INSERT_IDLE_FLAG, CLK_COR_KEEP_IDLE, CLK_COR_REPEAT_WAIT These attributes help control how clock correction is implemented. RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v2.3.2) June 24, 2004 1-800-255-7778...

  • Page 76: Clk_Cor_Insert_Idle_Flag

    For some applications, it is beneficial to know if incoming data is valid or not, and if the MGT is synchronized on the data. For applications using the 8B/10B encoding scheme, the www.xilinx.com RocketIO™ Transceiver User Guide 1-800-255-7778 UG024 (v2.3.2) June 24, 2004...

  • Page 77: Ports And Attributes

    This is intended to give early warning of possible problems well before corrupt data appears on RXDATA. RX_LOSS_OF_SYNC_FSM, a TRUE/FALSE attribute, indicates what the output of the RXLOSSOFSYNC port (see below) means. RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v2.3.2) June 24, 2004...

  • Page 78: Rxlossofsync

    FSM goes to state LOSS_OF_SYNC. LOSS_OF_SYNC (RXLOSSOFSYNC = 10) The FSM remains in this state until a comma is received, at which time it goes to state RESYNC. www.xilinx.com RocketIO™ Transceiver User Guide 1-800-255-7778 UG024 (v2.3.2) June 24, 2004...

  • Page 79: Channel Bonding (Channel Alignment)

    2-22. To ensure that the channels remain properly aligned following the channel bonding operation, the Master transceiver must also control the clock correction operations described in the previous section for all channel-bonded transceivers. RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v2.3.2) June 24, 2004...

  • Page 80: Channel Bonding (Alignment) Operation

    CHAN_BOND_WAIT = 8 CHAN_BOND_OFFSET = CHAN_BOND_WAIT CHAN_BOND_LIMIT = 2 x CHAN_BOND_WAIT Lower values are not recommended. Use higher values only if channel bonding sequences are farther apart than 17 bytes. www.xilinx.com RocketIO™ Transceiver User Guide 1-800-255-7778 UG024 (v2.3.2) June 24, 2004...

  • Page 81: Ports And Attributes

    GT_CUSTOM is the only primitive allowing modification to the sequence. These sequences are comprised of one or two sequences of length up to 4 bytes each, as set by CHAN_BOND_SEQ_LEN and CHAN_BOND_SEQ_2_USE. RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v2.3.2) June 24, 2004...

  • Page 82: Chan_Bond_Wait = 8

    CHAN_BOND_WAIT. CHBONDDONE This port indicates when a channel alignment has occurred in the MGT. When it is asserted, RXDATA is valid after RXCLKCORCNT goes to a 101. www.xilinx.com RocketIO™ Transceiver User Guide 1-800-255-7778 UG024 (v2.3.2) June 24, 2004...

  • Page 83: Chbondi, Chbondo

    CBS before or after the expected one. CRC (Cyclic Redundancy Check) Overview Cyclic Redundancy Check (CRC) is a procedure to detect errors in the received data. The RocketIO transceiver CRC logic supports the 32-bit invariant CRC calculation used by Infiniband, Fibre Channel, and Gigabit Ethernet.

  • Page 84: Crc Generation

    CRC Generation RocketIO transceivers support a 32-bit invariant CRC (fixed 32-bit polynomial shown below) for Gigabit Ethernet, Fibre Channel, Infiniband, and user-defined modes. The CRC recognizes the SOP (Start of Packet), EOP (End of Packet), and other packet features to identify the beginning and end of data.

  • Page 85: Ports And Attributes

    FIBRE_CHAN The FIBRE_CHAN CRC is similar to USER_MODE CRC (Figure 2-24), with one exception: In FIBRE_CHAN, SOP and EOP are predefined protocol delimiters. Unlike USER_MODE, RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v2.3.2) June 24, 2004 1-800-255-7778...
  • Page 86 Figure 2-25: Ethernet Mode Designs should generate only the /K28.5/D16.2/ IDLE sequence for transmission, never /K28.5/D5.6/. When the RocketIO CRC determines that the running disparity must be inverted to satisfy Gigabit Ethernet requirements, it will convert the first /K28.5/D16.2/ IDLE following a packet to /K28.5/D5.6/, performing the necessary conversion.
  • Page 87 The size of these headers is shown in Table 2-21. Table 2-21: Global and Local Headers Packet Description Size Local Routing Header 8 Bytes Global Routing Header 40 Bytes IBA Transport Header 12 Bytes RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v2.3.2) June 24, 2004 1-800-255-7778...

  • Page 88: Crc_Start_Of_Packet

    This should cause the receiver to register that a CRC error has occurred. RocketIO CRC Support Limitations There are limitations to the CRC support provided by the RocketIO transceiver core: • RocketIO CRC support is implementable for single-channel use only. Computation and byte- striping of CRC across multiple bonded channels is not supported.

  • Page 89: Fabric Interface (Buffers)

    Fabric Interface (Buffers) • The RocketIO transceiver does not compute the 16-bit variant CRC used for Infiniband, and thus does not fulfill the Infiniband CRC requirement. Infiniband CRC can be computed in the FPGA fabric. • All CRC formats have minimum allowable packet sizes. These limits are larger than those set by the user mode, and are defined by the specific protocol.

  • Page 90: Rx_Buffer_Use

    50Ω (default) or 75Ω impedance. Transmit Termination On-chip termination is provided at the transmitter, eliminating the need for external termination. Programmable options exist for 50Ω (default) and 75Ω termination. www.xilinx.com RocketIO™ Transceiver User Guide 1-800-255-7778 UG024 (v2.3.2) June 24, 2004...

  • Page 91: Rxpolarity Txinhibit

    (TXN, Normal Mode TXP) and are sent to another transceiver without being sent to its own receiver logic. During normal operation, LOOPBACK should be set to 00. RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v2.3.2) June 24, 2004 1-800-255-7778...

  • Page 92: Other Important Design Notes

    Other Important Design Notes Receive Data Path 32-bit Alignment The RocketIO transceiver uses the attribute ALIGN_COMMA_MSB to align protocol delimiters with the use of comma characters (special K-characters K28.5, K28.1, and K28.7 for most protocols). Setting ALIGN_COMMA_MSB to TRUE/FALSE determines where the comma characters appear on the RXDATA bus.

  • Page 93: Other Important Design Notes

    A properly aligned data flow is shown in Figure 2-29. TXDATA BC95B5B5 FDB53737 45674893 nnnnnnnn nnnnnnnn RXDATA BC95B5B5 FDB53737 45674893 nnnnnnnn nnnnnnnn ALIGNED_DATA pppppppp BC95B5B5 FDB53737 45674893 nnnnnnnn ug024_33_091602 Figure 2-29: RXDATA Aligned Correctly RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v2.3.2) June 24, 2004 1-800-255-7778...

  • Page 94: Bit Alignment Design

    RXCHARISCOMMA for comma detection. Verilog /********************************************************************* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION “AS IS” AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,...
  • Page 95 // aligned_data[31:0] -- Properly aligned 32-bit ALIGNED_DATA // sync -- Indicator that aligned_data is properly aligned // aligned_rxisk[3:0] - properly aligned 4 bit RXCHARISK // Inputs - These are all RocketIO inputs or outputs // as indicated: // usrclk2 -- RXUSRCLK2...
  • Page 96 ( rxchariscomma3 | rxchariscomma1 ) ) sync <= 1'b1; // This process generates aligned_data with commas aligned in [31:24], // assuming that incoming commas are aligned to [31:24] or [15:8]. www.xilinx.com RocketIO™ Transceiver User Guide 1-800-255-7778 UG024 (v2.3.2) June 24, 2004...

  • Page 97: Vhdl

    -- * -- *********************************************************** -- *********************************************************** -- * -- * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION “AS IS” -- * AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND -- * SOLUTIONS FOR XILINX DEVICES.
  • Page 98 -- aligned_data[31:0] -- Properly aligned 32-std_logic ALIGNED_DATA -- sync -- Indicator that aligned_data is properly aligned -- aligned_rxisk[3:0] -properly aligned 4-std_logic RXCHARISK -- Inputs - These are all RocketIO inputs or outputs -- as indicated: -- usrclk2 -- RXUSRCLK2 -- rxreset -- RXRESET...
  • Page 99 -- should be properly aligned, with the comma -- in aligned_data[31:24]. Output aligned_data is -- considered to be in sync when a comma is seen -- on rxdata (as indicated RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v2.3.2) June 24, 2004 1-800-255-7778...
  • Page 100 <= '1'; ELSE rxdata_hold(31 DOWNTO 0) <= rxdata(31 DOWNTO 0); rxisk_hold(3 DOWNTO 0) <= rxisk(3 DOWNTO 0); END IF; END IF; END IF; END PROCESS; END ARCHITECTURE translated; www.xilinx.com RocketIO™ Transceiver User Guide 1-800-255-7778 UG024 (v2.3.2) June 24, 2004...

  • Page 101: Serial I/O Description

    TXN pin GNDA UG024_46_021704 Figure 3-1: Differential Amplifier The RocketIO transceiver is implemented in Current Mode Logic (CML). A CML output consists of transistors configured as shown in Figure 3-1. CML uses a positive supply and offers easy interface requirements. In this configuration, both legs of the driver, V...

  • Page 102: Pre-Emphasis Techniques

    LOGIC or normal level (i.e., no pre-emphasis). A second characteristic of RocketIO transceiver pre-emphasis is that the STRONG level is reduced after some time to the LOGIC level, thereby minimizing the voltage swing necessary to switch the differential pair into the opposite state.
  • Page 103 Pre-emphasis Techniques UG024_17_020802 Figure 3-2: Alternating K28.5+ with No Pre-Emphasis Logic High Strong High Logic Low Strong Low UG024_18_020802 Figure 3-3: K28.5+ with Pre-Emphasis RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v2.3.2) June 24, 2004 1-800-255-7778...
  • Page 104 Chapter 3: Analog Design Considerations ug024_36_031803 Figure 3-4: Eye Diagram, 10% Pre-Emphasis, 20" FR4, Worst-Case Conditions ug024_37_031803 Figure 3-5: Eye Diagram, 33% Pre-Emphasis, 20" FR4, Worst-Case Conditions www.xilinx.com RocketIO™ Transceiver User Guide 1-800-255-7778 UG024 (v2.3.2) June 24, 2004...

  • Page 105: Differential Receiver

    (ITU). Jitter is typically expressed in a decimal fraction of Unit Interval (UI), e.g. 0.3 UI. Total Jitter = Deterministic Jitter (DJ) + Random Jitter (RJ). RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v2.3.2) June 24, 2004 1-800-255-7778...

  • Page 106: Clock And Data Recovery

    The serial transceiver input is locked to the input data stream through Clock and Data Recovery (CDR), a built-in feature of the RocketIO transceiver. CDR keys off the rising and falling edges of incoming data and derives a clock that is representative of the incoming data rate.

  • Page 107: Pcb Design Requirements

    FIFO acts much like a pass-through buffer. PCB Design Requirements To ensure reliable operation of the RocketIO transceivers, certain requirements must be met by the designer. This section outlines these requirements governing power filtering networks, high-speed differential signal traces, and reference clocks.
  • Page 108 RocketIO transceiver is interfacing with a transceiver from another vendor, termination voltage may be dictated by the specifications of the other transceiver. In cases where the RocketIO transceiver is interfacing with another RocketIO transceiver, any termination voltage my be used.

  • Page 109: Passive Filtering

    PCB; those labeled “Internal” denote a device that contains all necessary 0.22 µF capacitors for RocketIO power pins. Table boxes that say “No MGTs” denote a device that does not have any RocketIO transceivers.
  • Page 110 Chapter 3: Analog Design Considerations Table 3-6: Device and Package Combinations showing Devices with RocketIO Power Filtering Capacitors Internal to the Package and Externally Mounted on the PCB XC2VP2 XC2VP4 XC2VP7 XC2VP20 XC2VP30 XC2VP40 XC2VP50 XC2VP70 XC2VP100 FG256 External External...
  • Page 111 “L[n]” locations; the capacitors are mounted at the eight “C[n]” locations. Figure 3-10: Example Power Filtering PCB Layout for Four MGTs, In Device with External Capacitors, Top Layer RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v2.3.2) June 24, 2004...

  • Page 112: High-Speed Serial Trace Design

    High-Speed Serial Trace Design Routing Serial Traces All RocketIO transceiver I/Os are placed on the periphery of the BGA package to facilitate routing and inspection (since JTAG is not available on serial I/O pins). Two output/input impedance options are available in the RocketIO transceivers: 50Ω and 75Ω. Controlled impedance traces with a corresponding impedance should be used to connect the RocketIO transceiver to other compatible transceivers.

  • Page 113: Differential Trace Design

    TTL and other similarly noisy standards. The RocketIO transceiver is designed to function at 3.125 Gb/s through 40 inches of PCB with two high-bandwidth connectors. Longer trace lengths require either a low-loss dielectric or considerably wider serial traces.

  • Page 114: Ac And Dc Coupling

    UG024_23_042503 Figure 3-15: AC-Coupled Serial Link DC coupling (direct connection) is preferable in cases where RocketIO transceivers are interfaced with other RocketIO transceivers or other Mindspeed transceivers that have compatible differential and common mode voltage specifications. Passive components are not required when DC coupling is used.
  • Page 115 = 100Ω Differential UG024_24_042503 Figure 3-16: DC-Coupled Serial Link The RocketIO differential receiver produces the best bit-error rates when its common-mode voltage falls between 1.6V and 1.8V. When the receiver is AC-coupled to the line, V is the sole determinant of the receiver common-mode voltage, and therefore must be set to a value within this range.

  • Page 116: Reference Clock

    Figure 3-20. LV1145B LVDS 100Ω 2.5V-LVDS UG024_025b_050102 Figure 3-19: LVDS Reference Clock Oscillator Interface LV1145B LVDS_25_DCI 2.5V-LVDS 100Ω UG024_025d_112202 Figure 3-20: LVDS Reference Clock Oscillator Interface (On-Chip Termination) www.xilinx.com RocketIO™ Transceiver User Guide 1-800-255-7778 UG024 (v2.3.2) June 24, 2004...

  • Page 117: Powering The Rocketio Transceivers

    Other Important Design Notes Powering the RocketIO Transceivers IMPORTANT! All RocketIO transceivers in the FPGA, whether instantiated in the design or not, must be connected to power and ground. Unused transceivers may be powered by any 2.5 V source, and passive filtering is not required.
  • Page 118 Chapter 3: Analog Design Considerations www.xilinx.com RocketIO™ Transceiver User Guide 1-800-255-7778 UG024 (v2.3.2) June 24, 2004...

  • Page 119: Simulation Models

    Slave_2_hops setting. Figure 4-2 shows the channel bonding mode and linking for a 2VP50, which (optionally) contains more transceivers (16) per chip. RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v2.3.2) June 24, 2004 1-800-255-7778...
  • Page 120 CHBONDO CHBONDI CHBONDO CHBONDI CHBONDO CHBONDI CHBONDO CHBONDI CHBONDO CHBONDI CHBONDO CHBONDI CHBONDO CHBONDI CHBONDO CHBONDI SLAVE_2_HOPS SLAVE_2_HOPS SLAVE_2_HOPS SLAVE_1_HOP SLAVE_2_HOPS SLAVE_2_HOPS SLAVE_2_HOPS SLAVE_2_HOPS UG024_08_020802 Figure 4-2: 2VP50 Implementation www.xilinx.com RocketIO™ Transceiver User Guide 1-800-255-7778 UG024 (v2.3.2) June 24, 2004...

  • Page 121: Mgt Package Pins

    AF12, AF11, AB15, AB16 AF10, AF9 GT_X2_Y1 A13, A14, A15, A12, A11, A10, GT_X3_Y0 AB17, AB18, AF7, AF6, AB19, AB20 AF5, AF4 GT_X3_Y1 A17, A18, A19, A7, A6, A5, A4 RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v2.3.2) June 24, 2004 1-800-255-7778...
  • Page 122 A5, A4, A3, A13, A12, A11, A10 GT_X6_Y0 AP9, AP8, AP7, AP6 GT_X6_Y1 A9, A8, A7, GT_X7_Y0 AP5, AP4, AP3, AP2 GT_X7_Y1 A5, A4, A3, GT_X8_Y0 GT_X8_Y1 GT_X9_Y0 GT_X9_Y1 www.xilinx.com RocketIO™ Transceiver User Guide 1-800-255-7778 UG024 (v2.3.2) June 24, 2004...
  • Page 123 BB9, BB8, BB7, AW5, AW4 GT_X9_Y1 A7, A6, A5, A4 A5, A4, A3, A2 A9, A8, A7, A6 GT_X10_Y0 BB5, BB4, BB3, GT_X10_Y1 A5, A4, A3, A2 GT_X11_Y0 GT_X11_Y1 RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v2.3.2) June 24, 2004 1-800-255-7778...
  • Page 124 Chapter 4: Simulation and Implementation www.xilinx.com RocketIO™ Transceiver User Guide 1-800-255-7778 UG024 (v2.3.2) June 24, 2004...
  • Page 125 Figure A-1.) The model presented in this section treats the RocketIO core as a “black box.” Propagation delays internal to the RocketIO core logic are ignored. Signals are characterized with setup and hold times for inputs, and with clock to valid output times for outputs.
  • Page 126 Appendix A: RocketIO Transceiver Timing Model PACKAGE PINS MULTI-GIGABIT TRANSCEIVER CORE FPGA FABRIC AVCCAUXRX Power Down 2.5V RX POWERDOWN RXRECCLK VTRX Termination Supply RX RXPOLARITY RXREALIGN RXCOMMADET ENPCOMMAALIGN ENMCOMMAALIGN RXCHECKINGCRC Check RXCRCERR RXDATA[15:0] RXDATA[31:16] RXNOTINTABLE[3:0] Comma Elastic RXDISPERR[3:0] Detect Deserializer...

  • Page 127: Timing Parameters

    Setup/Hold Times of Inputs Relative to Clock Basic Format: ParameterName_SIGNAL where ParameterName = T with subscript string defining the timing relationship SIGNAL name of RocketIO signal synchronous to the clock ParameterName Format: Setup time before clock edge GxCK Hold time after clock edge GCKx where...

  • Page 128: Clock Pulse Width

    The following four tables list the timing parameters as reported by the implementation tools relative to the clocks given in Table A-1, along with the RocketIO signals that are synchronous to each clock. (No signals are synchronous to REFCLK or TXUSRCLK.) A timing diagram (Figure A-2) illustrates the timing relationships.
  • Page 129 GCKC _TCRCE/T _TCRCE Control inputs TXFORCECRCERR GCCK GCKC _TPOL/T _TPOL Control inputs TXPOLARITY GCCK GCKC _TINH/T _TINH Control inputs TXINHIBIT GCCK GCKC _LBK/T _LBK Control inputs LOOPBACK[1:0] GCCK GCKC RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v2.3.2) June 24, 2004 1-800-255-7778...
  • Page 130 Clock pulse width, Low state TXUSRCLK TX2PWL Notes: 1. REFCLK is not synchronous to any RocketIO signals. 2. BREFCLK is not synchronous to any RocketIO signals. 3. TXUSRCLK is not synchronous to any RocketIO signals. www.xilinx.com RocketIO™ Transceiver User Guide 1-800-255-7778 UG024 (v2.3.2) June 24, 2004...
  • Page 131 GWL x GWH CLOCK GCCK GCKC CONTROL INPUTS GCKCO CONTROL OUTPUTS GCKDO DATA OUTPUTS GDCK GCKD DATA INPUTS UG012_106_02_100101 Figure A-2: RocketIO Transceiver Timing Relative to Clock Edge RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v2.3.2) June 24, 2004 1-800-255-7778...
  • Page 132 Appendix A: RocketIO Transceiver Timing Model www.xilinx.com RocketIO™ Transceiver User Guide 1-800-255-7778 UG024 (v2.3.2) June 24, 2004...

  • Page 133: Valid Data Characters

    011100 0100 D15.0 000 01111 010111 0100 101000 1011 D16.0 000 10000 011011 0100 100100 1011 D17.0 000 10001 100011 1011 100011 0100 D18.0 000 10010 010011 1011 010011 0100 RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v2.3.2) June 24, 2004 1-800-255-7778...
  • Page 134 101100 1001 D14.1 001 01110 011100 1001 011100 1001 D15.1 001 01111 010111 1001 101000 1001 D16.1 001 10000 011011 1001 100100 1001 D17.1 001 10001 100011 1001 100011 1001 www.xilinx.com RocketIO™ Transceiver User Guide 1-800-255-7778 UG024 (v2.3.2) June 24, 2004...
  • Page 135 001101 0101 D13.2 010 01101 101100 0101 101100 0101 D14.2 010 01110 011100 0101 011100 0101 D15.2 010 01111 010111 0101 101000 0101 D16.2 010 10000 011011 0101 100100 0101 RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v2.3.2) June 24, 2004 1-800-255-7778...
  • Page 136 110100 0011 D12.3 011 01100 001101 1100 001101 0011 D13.3 011 01101 101100 1100 101100 0011 D14.3 011 01110 011100 1100 011100 0011 D15.3 011 01111 010111 0011 101000 1100 www.xilinx.com RocketIO™ Transceiver User Guide 1-800-255-7778 UG024 (v2.3.2) June 24, 2004...
  • Page 137 001101 0010 D13.4 100 01101 101100 1101 101100 0010 D14.4 100 01110 011100 1101 011100 0010 D15.4 100 01111 010111 0010 101000 1101 D16.4 100 10000 011011 0010 100100 1101 RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v2.3.2) June 24, 2004 1-800-255-7778...
  • Page 138 101100 1010 D14.5 101 01110 011100 1010 011100 1010 D15.5 101 01111 010111 1010 101000 1010 D16.5 101 10000 011011 1010 100100 1010 D17.5 101 10001 100011 1010 100011 1010 www.xilinx.com RocketIO™ Transceiver User Guide 1-800-255-7778 UG024 (v2.3.2) June 24, 2004...
  • Page 139 011100 0110 D15.6 110 01111 010111 0110 101000 0110 D16.6 110 10000 011011 0110 100100 0110 D17.6 110 10001 100011 0110 100011 0110 D18.6 110 01010 010011 0110 010011 0110 RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v2.3.2) June 24, 2004 1-800-255-7778...
  • Page 140 101000 1110 D16.7 111 10000 011011 0001 100100 1110 D17.7 111 10001 100011 0111 100011 0001 D18.7 111 10010 010011 0111 010011 0001 D19.7 111 10011 110010 1110 110010 0001 www.xilinx.com RocketIO™ Transceiver User Guide 1-800-255-7778 UG024 (v2.3.2) June 24, 2004...

  • Page 141: Valid Control Characters (K-Characters)

    001001 0111 K29.7 111 11101 101110 1000 010001 0111 K30.7 111 11110 011110 1000 100001 0111 Notes: 1. Used for testing and characterization only. Do not use in protocols. RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v2.3.2) June 24, 2004 1-800-255-7778...
  • Page 142 Appendix B: 8B/10B Valid Characters www.xilinx.com RocketIO™ Transceiver User Guide 1-800-255-7778 UG024 (v2.3.2) June 24, 2004...

  • Page 143: Application Notes

    125 MHz is serialized and retransmitted at 2.5 Gb/s. At a 156.25 MHz input, the output is at its maximum speed of 3.125 Gb/s. The parallel data stream applied to the RocketIO transceiver can either be 20 bits direct, or it can be written as 16 bits, to which 8b/10b coding is applied to generate the 20 bits required.

  • Page 144: Xapp652: Word Alignment And Sonet/Sdh Deframing

    This application note describes the implementation of a RocketIO transceiver bit-error rate tester (BERT) reference design demonstrating a serial link (1.0 Gb/s to 3.125 Gb/s) between two RocketIO multi-gigabit transceivers (MGT) embedded in a single Virtex-II Pro FPGA. To build a system, an IBM CoreConnect™ infrastructure connects the PowerPC™405 processor (PPC405) to external memory and other peripherals using the processor local bus (PLB) and device control register (DCR) buses.

  • Page 145: Rocketio Transceivers

    This application note describes a design that reduces latency through the receive elastic buffer of the Virtex-II Pro™ RocketIO™ transceiver. This note is only applicable for designs that do not use the clock correction or channel bonding features of the RocketIO transceiver. (These operations can still be done in the fabric, if needed).

  • Page 146: Xapp687: 64B/66B Encoder/Decoder

    Each MGT has separate transmit and receive functions (full-duplex) and can be operated at baud rates from 600 Mb/s to 3.125 Gb/s. Additionally, every RocketIO MGT block is fully independent and contains a complete set of common SerDes (serializer/deserializer) functions.

  • Page 147: White Papers

    Instruments™ TLK3101, and the Mindspeed™ CX27201. The features offered by each of these devices are presented, along with a discussion of how the RocketIO transceiver can afford an alternative to each multi-chip solution. Links to Xilinx information resources for the Virtex-II Pro Platform FPGA and embedded RocketIO transceiver are presented in the final section.
  • Page 148 Appendix C: Related Online Documents www.xilinx.com RocketIO™ Transceiver User Guide 1-800-255-7778 UG024 (v2.3.2) June 24, 2004...

  • Page 149: Index

    32-bit alignment design DEC_PCOMMA_DETECT overview 4-byte clock DEC_VALID_COMMA_ONLY ports and attributes VHDL MCOMMA_10B_VALUE Clock/Data Recovery (CDR) parameters 1-byte clock MCOMMA_DETECT Clocking 2-byte clock PCOMMA_10B_VALUE clock and data recovery 32-bit alignment design RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v2.3.2) June 24, 2004 1-800-255-7778...

  • Page 150: Receive Data Path 32-Bit Alignment

    (Epson), for LVPECL synchronization logic Transmitter and Elastic (Receiver) Buffers oscillator (Pletronics), for LVDS Ports (defined) Transmitter Buffer (FIFO) Reset/Power Down CHBONDDONE RocketIO transceiver CHBONDI additional resources CHBONDO analog design considerations www.xilinx.com RocketIO™ Transceiver User Guide 1-800-255-7778 UG024 (v2.3.2) June 24, 2004...
  • Page 151 User Guide conventions online references port and attribute names typographical Vitesse Disparity Example Voltage Regulation RocketIO™ Transceiver User Guide www.xilinx.com UG024 (v2.3.2) June 24, 2004 1-800-255-7778...
  • Page 152 RocketIO™ Transceiver User Guide 1-800-255-7778 UG024 (v2.3.2) June 24, 2004...

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