Xilinx 7 Series User Manual page 184

Chapter 4: Receiver
X-Ref Target - Figure 4-41
Figure 4-42
184
Send Feedback
RXSYNCALLIN
RXSYNCIN
RXSYNCMODE
1'b1
RXDLYSRESET
RXSYNCALLIN
RXSYNCIN
RXSYNCMODE
1'b0
RXDLYSRESET
Figure 4-41: RX Buffer Bypass—Multi-Lane Auto Mode Port Connection
shows the required steps to perform auto RX phase and delay alignment.
www.xilinx.com
RXPHALIGNDONE
RXSYNCOUT
Master
RXSYNCDONE
RXPHALIGNDONE
RXSYNCOUT
Slave
RXSYNCDONE
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
UG482_c4_141_020613