Xilinx 7 Series User Manual page 98

Chapter 3: Transmitter
Table 3-16: TX Buffer Attributes (Cont'd)
Attribute
TXSYNC_OVRD
LOOPBACK_CFG
TX Buffer Bypass Use Modes
TX phase alignment can be performed on one channel (single lane) or a group of channels sharing a
single TXOUTCLK (multi-lane). For GTP transceivers, TX buffer bypass supports single-lane and
multi-lane applications (see
Table 3-17: TX Buffer Bypass Use Modes
Using TX Buffer Bypass in Single-Lane Mode
These GTP transceiver settings should be used to bypass the TX buffer:
•
•
•
With the GTP transceiver reference clock selected, TXOUTCLK is used as the source of the
TXUSRCLK. The user must ensure that TXOUTCLK and the selected GTP transceiver reference
clock are operating at the desired frequency. When the TX buffer is bypassed, the TX phase
alignment procedure must be performed after these conditions:
•
•
•
•
98
Send Feedback
Type
1-bit Binary Reserved. Tie to 1'b1.
1-bit Binary Reserved. The recommended value from the 7 Series FPGAs Transceivers Wizard
should be used.
Table
TX Buffer Bypass
Single Lane
Multi-lane
TXBUF_EN = FALSE
TX_XCLK_SEL = TXUSR
TXOUTCLKSEL = 3'b011 or 3'b100 to select the GTP transceiver reference clock as the
source of TXOUTCLK
Resetting or powering up the GTP transceiver TX
Resetting or powering up the PLL
Change of the GTP transceiver reference clock source or frequency
Change of the TX line rate
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Description
3-17).
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016