Xilinx 7 Series User Manual page 288

Appendix D: DRP Address Map of the GTP Transceiver
Table D-2: DRP Map of GTPE2_CHANNEL Primitive (Cont'd)
DRP
DRP Bits
Address
15:0
0036
15:0
0037
15:0
0038
15:0
0039
15:0
003A
15:11
003B
8:0
003B
11:0
003C
15
003D
14
003D
13
003D
12
003D
9
003D
8
003D
5:0
003D
9:0
003E
9:0
003F
15:14
0040
9:0
0040
14:13
0041
12:8
0041
288
Send Feedback
R/W Attribute Name
R/W ES_SDATA_MASK
R/W ES_SDATA_MASK
R/W ES_SDATA_MASK
R/W ES_SDATA_MASK
R/W ES_SDATA_MASK
R/W ES_PRESCALE
R/W ES_VERT_OFFSET
R/W ES_HORZ_OFFSET
R/W RX_DISPERR_SEQ_MATCH
R/W DEC_PCOMMA_DETECT
R/W DEC_MCOMMA_DETECT
R/W DEC_VALID_COMMA_ONLY
R/W ES_ERRDET_EN
R/W ES_EYE_SCAN_EN
R/W ES_CONTROL
R/W ALIGN_COMMA_ENABLE
R/W ALIGN_MCOMMA_VALUE
R/W RXSLIDE_MODE
R/W ALIGN_PCOMMA_VALUE
R/W ALIGN_COMMA_WORD
R/W RX_SIG_VALID_DLY
www.xilinx.com
Attribute Attribute
Bits Encoding
15:0 0-65535
31:16 0-65535
47:32 0-65535
63:48 0-65535
79:64 0-65535
4:0 0-31
8:0 0-511
11:0 0-4095
FALSE
0
TRUE
FALSE
0
TRUE
FALSE
0
TRUE
FALSE
0
TRUE
FALSE
0
TRUE
FALSE
0
TRUE
5:0 0-63
9:0 0-1023
9:0 0-1023
OFF
AUTO
1:0
PCS
PMA
9:0 0-1023
1
1:0
2
1
4:0
2
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
DRP
Encoding
0-65535
0-65535
0-65535
0-65535
0-65535
0-31
0-511
0-4095
0
1
0
1
0
1
0
1
0
1
0
1
0-63
0-1023
0-1023
0
1
2
3
0-1023
1
2
0
1