Xilinx RocketIO Manuals

Manuals and User Guides for Xilinx RocketIO. We have 4 Xilinx RocketIO manuals available for free PDF download: User Manual

Xilinx RocketIO User Manual (204 pages)

Brand: Xilinx | Category: Transceiver | Size: 2.13 MB

User Guide
1
Table of Contents
7
Chapter 1: Rocketio X Transceiver Overview

21
Chapter 3: Clocking and Clock Domains

21
Chapter 2: Digital Design Considerations

41
- Chapter 2: Digital Design Considerations
  42
- Top-Level Architecture
  42
- Block Level Functions
  43
  - Classification of Signals and Overloading
    43
    
    Static Signals (Control Inputs)
    43
    
    Table 2-1: PCS Interface Choice
    43
    
    Dynamic Signals
    44
  - Bus Interface
    46
    
    Clock Ratio
    46
    
    Selecting the External Configuration (Fabric Interface)
    46
    
    Selecting the Internal Configuration
    46
    
    Table 2-2: Selecting the External Configuration
    46
    
    Table 2-3: Selecting the Internal Configuration
    46
    
    Table 2-4: Data Width Clock Ratios
    46
  - 8B/10B
    47
    
    B/10B
    47
    
    Figure 2-3: 8B/10B Parallel-To-Serial Conversion
    47
    
    Figure 2-4: 4-Byte Serial Structure
    47
    
    Encoder
    48
    
    Table 2-5: Running Disparity Control
    48
    
    Figure 2-5: 10-Bit TX Data Map with 8B/10B Bypassed
    49
    
    Table 2-6: 8B/10B Bypassed Signal Significance
    49
    
    Decoder
    50
    
    Figure 2-6: 10-Bit RX Data Map with 8B/10B Bypassed
    50
    
    RXCHARISK and RXRUNDISP
    51
    
    Rxdisperr
    51
    
    Rxnotintable
    51
    
    Table 2-7: 8B/10B Bypassed Signal Significance
    51
  - Vitesse Disparity Example
    52
  - Comma Detection
    53
    
    Bypass
    53
    
    Summary
    53
    
    Symbol Detection
    53
    
    Setting MCOMMA_10B_VALUE, PCOMMA_10B_VALUE, and COMMA_10B_MASK (Special Note)
    54
    
    Table 2-8: Symbol Detection
    54
    
    Alignment
    55
    
    Figure 2-7: 8B/10B Comma Detection Example
    55
    
    Table 2-9: Data Alignment
    55
  - 64B/66B
    57
    
    Encoder
    57
    
    Table 2-10: 64B/66B Bypassing
    57
    
    Table 2-11: Transmit 64B/66B Encoder Control Mapping
    57
- Operation Modes
  43
- Chapter 2: Digital Design Considerations
  58
- Figure 2-8: Block Format Function
  58
- Scrambler
  59
- Table 2-12: Control Codes
  59
- Decoder
  60
- Descrambler
  60
- Gearbox
  60
- Block Sync
  61
- Chapter 3: Clocking and Clock Domains
  73
  - Clock Domain Architecture
    73
    
    Figure 3-1: Reference Clock Selection
    73
    
    Reference Clocks
    73
    
    Clock Ports
    74
    
    Table 3-1: Clock Ports
    74
    
    1:1 Use Models
    75
    
    Figure 3-2: BREFCLK 0:1:1
    75
    
    Use Models
    75
    
    Figure 3-3: BREFCLK 1:1:1
    76
    
    Figure 3-4: BREFCLK 2:1:1
    76
    
    Figure 3-5: TXOUTCLK 1:1:1
    77
    
    Figure 3-6: RXRECCLK 1:1:1
    77
    
    2:1 Use Models
    78
    
    Figure 3-7: BREFCLK 1:2:1
    78
    
    Figure 3-8: BREFCLK 2:2:1
    78
    
    Figure 3-10: RXRECCLK 2:2:1
    79
    
    Figure 3-9: TXOUTCLK 2:2:1
    79
    
    1:2 Use Models
    80
    
    Figure 3-11: BREFCLK 0:1:2
    80
    
    Figure 3-12: BREFCLK 1:1:2
    80
    
    Figure 3-13: BREFCLK 2:1:2
    81
    
    Figure 3-14: TXOUTCLK 2:1:2
    81
    
    Figure 3-15: RXRECCLK 2:1:2
    82
    
    Supported Use Models for each PMA Mode
    83
    
    Table 3-2: Supported Use Models
    83
    
    Pma
    85
    
    Table 3-3: Supported Standards, Speeds, Bus Widths, and Frequencies for
    85
    
    Clock Dependency
    88
    
    Data Path Latency
    89
    
    Table 3-4: Latency through Various Transmitter Components/Processes
    89
    
    Table 3-5: Latency through Various Receiver Components/Processes
    89
  - Resets and Power down
    90
    
    PCS Reset
    90
    
    PCS/PMA Power down
    90
    
    Table 3-6: Power Control Descriptions
    90
Chapter 4: Analog Design Considerations

91
Chapter 5: Simulation and Implementation

123
- PMA Initialization
  123
- Chapter 5: Simulation and Implementation
  124
- Figure 5-1: PMA Initialization
  124
- Model Considerations
  125
- Simulation Models
  125
  - Smartmodels
    125
  - Hspice
    125
- MGT Package Pins
  126
- Table 5-1: LOC Grid and Package Pins Correlation for Ff896Package
  126
- Table 5-2: LOC Grid and Package Pins Correlation for FF1704 Packages
  126
- Diagnostic Signals
  127
  - Loopback
    127
    
    Table 5-3: LOOPBACK Modes
    127
    
    Parallel Loopback
    128
    
    Post/Pre-Driver Serial Loopback
    128
    
    Table 5-4: Recommended Settings for Serial Loopback
    128
Appendix A: Rocketio X Transceiver Timing Model

129
- Table A-1: Rocketio X Clock Descriptions
  129
Appendix A: Rocketio X Transceiver Timing Model

130
Appendix B: 8B/10B Valid Characters

138
- Table B-2: Valid Control "K" Characters
  145
Appendix C: PMA Attribute Programming Bus

147
- Interface Description
  147
- Table C-1: PMA Attribute Bus Ports
  147
- Memory Map
  148
- Figure C-1: PMA Attribute Bus Waveform
  148
Appendix C: PMA Attribute Programming Bus

148
- Table C-2: PMA Attribute Memory Map
  148
- Register Definition
  149
  - Masterbias[1:0]
    149
  - Vcodac[5:0]
    149
  - Txdivratio[9:0]
    149
  - Table C-3: MASTERBIAS[1:0] Definition
    149
  - Table C-4: TX Clock Multiplier Ratio Definition
    149
  - Table C-5: TXCLK0 Divider Ratio Definition
    150
  - Table C-6: TXOUTCLK Divider Ratio Definition
    150
  - Txbuswid
    151
  - Txloopfilterc[1:0]
    151
  - Txloopfilterr[1:0]
    151
  - Table C-7: TXBUSWID Definition
    151
  - Table C-8: TXLOOPFILTERC[1:0] Definition
    151
  - Table C-9: TXLOOPFILTERR[1:0] Definition
    151
  - Iboost
    152
  - Txcpi
    152
  - Txvcodac
    152
  - Table C-10: IBOOST Definition
    152
  - Table C-11: TXCPI Definition
    152
  - Table C-12: TXVCODAC Definition
    152
  - Txvcogain
    153
  - Txvsel[1:0]
    153
  - Txreg[1:0]
    153
  - Txdownlevel[3:0]
    153
  - Table C-13: TXVCOGAIN Definition
    153
  - Table C-14: TXVSEL[1:0] Definition
    153
  - Table C-15: TXREG[1:0] Definition
    153
  - Prdrvoff
    154
  - Empoff
    154
  - Slew
    154
  - Txemphlevel[3:0]
    154
  - Table C-16: PRDRVOFF Definition
    154
  - Table C-17: EMPOFF Definition
    154
  - Table C-18: SLEW Definition
    154
  - Txdigsw
    155
  - Txanasw
    155
  - Rxdivratio[13:0]
    155
  - Table C-19: TXDIGSW Definition
    155
  - Table C-20: TXANASW Definition
    155
  - Table C-21: RX Clock Multiplier Ratio Definition
    155
  - Table C-22: RXCLK0 Divider Ratio Definition
    156
  - Table C-23: RXRECCLK Divider Ratio Definition
    156
  - Rxloopfilterc[1:0]
    157
  - Table C-24: VCO Divider Ratio Definition
    157
  - Table C-25: BREFCLK Divider Ratio Definition
    157
  - Table C-26: RXLOOPFILTERC[1:0] Definition
    157
  - Rxloopfilterr[2:0]
    158
  - Rxvcosw
    158
  - Rxcpi
    158
  - Rxvcodac
    158
  - Table C-27: RXLOOPFILTERR[2:0] Definition
    158
  - Table C-28: RXVCOSW Definition
    158
  - Table C-29: RXCPI[1:0] Definition
    158
  - Rxvcogain
    159
  - Rxvsel[1:0]
    159
  - Rxreg[1:0]
    159
  - Table C-30: RXVCODAC Definition
    159
  - Table C-31: RXVCOGAIN Definition
    159
  - Table C-32: RXVSEL[1:0] Definition
    159
  - Table C-33: RXREG[1:0] Definition
    159
  - Rxvselcp[1:0]
    160
  - Table C-34: RXVSELCP[1:0] Definition
    160
  - Rxcpgain
    161
  - Rxfltcpt[4:0]
    161
  - Vselafe[1:0]
    161
  - Rxfei[1:0]
    161
  - Table C-35: RXCPGAIN Definition
    161
  - Table C-36: VSELAFE[1:0] Definition
    161
  - Table C-37: RXFEI[1:0] Definition
    161
  - Rxfer[9:0]
    162
  - Rxflcpi[1:0]
    162
  - Biasen
    162
  - Txanaen
    162
  - Table C-38: RXFLCPI[1:0] Definition
    162
  - Table C-39: BIASEN Definition
    162
  - Table C-40: TXANAEN Definition
    162
  - Txdigen
    163
  - Rxanaen
    163
  - Txen
    163
  - Rxen
    163
  - Table C-41: TXDIGEN Definition
    163
  - Table C-42: RXANAEN Definition
    163
  - Table C-43: TXEN Definition
    163
  - Table C-44: RXEN Definition
    163
  - Txdrven
    164
  - Pmainit
    164
  - Sel_Dac_Tran[3:0]
    164
  - Sel_Dac_Fix[3:0]
    164
  - Endcd
    164
  - Afe_Flat_Enable
    164
- Data-Density Independent Phase Adjustment for CDR
  164
- Table C-45: TXDRVEN Definition
  164
- Figure C-2: Fine Loop Charge Pump
  165
- Table C-46: Tail Current Value Vs. Programmability Code
  165
- Figure C-3: Sampling Point Offset
  166
- Table C-47: Allowed Programmable Codes
  166

Xilinx RocketIO User Manual (156 pages)

Brand: Xilinx | Category: Transceiver | Size: 1.65 MB

User Guide
1
Table of Contents
7
Schedule of Figures

13
Schedule of Tables

15
Preface: about this Guide

17
- Rocketio Features
  
  17
- Guide Contents
  
  17
- For more Information
  
  18
- Additional Resources
  
  18
- Conventions
  
  19
  - Port and Attribute Names
    19
  - Typographical
    19
  - Online Document
    20
Chapter 1 : Rocketio Transceiver Overview

21
- Basic Architecture and Capabilities
  
  21
- Rocketio Transceiver Instantiations
  
  23
  - HDL Code Examples
    23
- List of Available Ports
  
  24
- Primitive Attributes
  
  29
- Modifiable Primitives
  
  34
- Byte Mapping
  
  38
Chapter 2: Digital Design Considerations

39
- Clocking
  
  39
  - Clock Signals
    39
    
    Brefclk
    41
  - Clock Ratio
    42
  - Digital Clock Manager (DCM) Examples
    42
    
    Example 1A: Two-Byte Clock with DCM
    43
    
    Example 1B: Two-Byte Clock Without DCM
    46
    
    Example 2: Four-Byte Clock
    46
    
    Example 3: One-Byte Clock
    50
  - Half-Rate Clocking Scheme
    54
  - Multiplexed Clocking Scheme with DCM
    55
  - Multiplexed Clocking Scheme Without DCM
    55
  - Rxrecclk
    56
  - Clock Dependency
    56
  - Data Path Latency
    57
- Reset/Power down
  
  57
- 8B/10B Encoding/Decoding
  
  60
  - Overview
    60
    
    8B/10B Encoder
    60
    
    8B/10B Decoder
    60
  - Ports and Attributes
    61
    
    Txbypass8B10B, Rx_Decode_Use
    61
    
    Txchardispval, Txchardispmode
    62
    
    Txcharisk
    63
    
    Txrundisp
    63
    
    Txkerr
    63
    
    Rxcharisk, Rxrundisp
    63
    
    Rxdisperr
    64
    
    Rxnotintable
    64
  - Vitesse Disparity Example
    64
    
    Transmitting Vitesse Channel Bonding Sequence
    64
    
    Receiving Vitesse Channel Bonding Sequence
    65
  - 8B/10B Bypass Serial Output
    65
  - 8B/10B Serial Output Format
    66
  - HDL Code Examples: Transceiver Bypassing of 8B/10B Encoding
    66
- SERDES Alignment
  
  67
  - Overview
    67
    
    Serializer
    67
    
    Deserializer
    67
  - Ports and Attributes
    67
    
    Align_Comma_Msb
    67
    
    Enpcommaalign, Enmcommaalign
    68
    
    Rocketio™ Transceiver User Guide Www.xilinx.com
    69
    
    Pcomma_Detect
    70
    
    Mcomma_Detect
    70
    
    Comma_10B_Mask
    70
    
    Pcomma_10B_Value
    70
    
    Mcomma_10B_Value
    70
    
    Dec_Mcomma_Detect Dec_Valid_Comma_Only
    70
    
    Rxrealign
    70
    
    Dec_Pcomma_Detect
    71
    
    Dec_Mcomma_Detect
    71
    
    Dec_Valid_Comma_Only
    71
    
    Rxchariscomma
    71
    
    Rxcommadet
    71
- Clock Recovery
  
  71
  - Overview
    71
    
    Clock Synthesizer
    71
    
    Clock and Data Recovery
    72
  - Clock Correction
    72
  - Ports and Attributes
    73
    
    Clk_Correct_Use
    73
    
    Rx_Buffer_Use
    74
    
    Clk_Cor_Seq_
    74
    
    Clk_Cor_Seq_Len
    75
    
    Clk_Cor_Insert_Idle_Flag
    75
    
    Clk_Cor_Keep_Idle
    75
    
    Clk_Cor_Repeat_Wait
    75
- Synchronization Logic
  
  76
  - Overview
    76
  - Ports and Attributes
    76
    
    Rxclkcorcnt
    76
    
    Rx_Los_Invalid_Incr Rx_Los_Threshold
    77
    
    Rx_Los_Threshold
    78
- Channel Bonding (Channel Alignment)
  
  79
  - Overview
    79
  - Channel Bonding (Alignment) Operation
    80
  - Ports and Attributes
    81
    
    Chan_Bond_Mode
    81
    
    Enchansync
    81
    
    Chan_Bond_One_Shot
    81
    
    Chan_Bond_Seq_
    81
    
    Chan_Bond__Seq_Len
    81
    
    Chan_Bond_Seq_2_Use
    81
    
    Chan_Bond_Wait
    82
    
    Chan_Bond_Offset
    82
    
    Chan_Bond_Limit
    82
    
    Chbonddone
    83
    
    Chbondi, Chbondo
    83
    
    Rxclkcorcnt, Rxlossofsync
    83
  - Troubleshooting
    83
- CRC (Cyclic Redundancy Check)
  
  84
  - Overview
    84
    
    CRC Operation
    84
    
    CRC Generation
    84
    
    CRC Latency
    85
  - Ports and Attributes
    85
    
    Tx_Crc_Use
    85
    
    Rx_Crc_Use
    85
    
    Crc_Format
    85
    
    Crc_Start_Of_Packet
    88
    
    Crc_End_Of_Packet
    88
    
    Rxcheckingcrc, Rxcrcerr
    88
    
    Txforcecrcerr, Tx_Crc_Force_Value
    89
  - Rocketio CRC Support Limitations
    89
- Fabric Interface (Buffers)
  
  89
  - Overview: Transmitter and Elastic (Receiver) Buffers
    89
    
    Transmitter Buffer (FIFO)
    89
    
    Receiver Buffer
    89
  - Ports and Attributes
    90
    
    Txbuferr
    90
    
    Tx_Buffer_Use
    90
    
    Rxbufstatus
    90
    
    Rx_Buffer_Use
    90
- Miscellaneous Signals
  
  90
  - Tx_Data_Width
    90
  - Serdes_10B
    90
  - Termination_Imp
    91
    
    Rxpolarity Txinhibit
    91
    
    Tx_Diff_Ctrl Pre_Emphasis
    91
  - Loopback
    91
- Other Important Design Notes
  
  93
  - Receive Data Path 32-Bit Alignment
    93
  - Bit Alignment Design
    95
    
    Verilog
    95
    
    Vhdl
    98
Chapter 3 : Analog Design Considerations

103
- Serial I/O Description
  
  103
- Pre-Emphasis Techniques
  
  104
  - Rocketio™ Transceiver User Guide Www.xilinx.com
    105
- Differential Receiver
  
  107
- Jitter
  
  107
  - Clock and Data Recovery
    108
- PCB Design Requirements
  
  109
  - Power Conditioning
    109
    
    Voltage Regulator Selection and Use
    109
    
    Termination Voltage
    110
    
    Passive Filtering
    111
  - High-Speed Serial Trace Design
    115
    
    Routing Serial Traces
    115
    
    Differential Trace Design
    116
    
    AC and DC Coupling
    117
  - Reference Clock
    119
    
    Epson EG-2121CA 2.5V (LVPECL Outputs)
    119
    
    Pletronics LV1145B (LVDS Outputs)
    119
  - Powering the Rocketio Transceivers
    120
- Other Important Design Notes
  
  120
  - Pin Connections on the Unused Rocketio Transceivers
    120
  - The POWERDOWN Port
    120
Chapter 4 : Simulation and Implementation

121
- Simulation Models
  
  121
  - Smartmodels
    121
  - Hspice
    121
- Implementation Tools
  
  121
- MGT Package Pins
  
  123

Xilinx RocketIO User Manual (124 pages)

Brand: Xilinx | Category: Transceiver | Size: 2.11 MB

Xilinx RocketIO User Manual (152 pages)

Brand: Xilinx | Category: Transceiver | Size: 1.49 MB

User Guide
1
Table of Contents
7
Schedule of Figures

13
Schedule of Tables

15
Preface: about this Guide

17
- Rocketio Features
  
  17
- Guide Contents
  
  17
- For more Information
  
  18
- Additional Resources
  
  18
- Conventions
  
  19
  - Port and Attribute Names
    19
  - Typographical
    19
  - Online Document
    20
Chapter 1 : Rocketio Transceiver Overview

21
- Basic Architecture and Capabilities
  
  21
- Rocketio Transceiver Instantiations
  
  23
  - HDL Code Examples
    23
- List of Available Ports
  
  24
- Primitive Attributes
  
  28
- Modifiable Primitives
  
  33
- Byte Mapping
  
  37
Chapter 2: Digital Design Considerations

39
- Clocking
  
  39
  - Clock Signals
    39
    
    Brefclk
    41
  - Clock Ratio
    43
  - Digital Clock Manager (DCM) Examples
    43
    
    Example 1A: Two-Byte Clock with DCM
    44
    
    Example 1B: Two-Byte Clock Without DCM
    47
    
    Example 2: Four-Byte Clock
    47
    
    Example 3: One-Byte Clock
    51
  - Half-Rate Clocking Scheme
    55
  - Multiplexed Clocking Scheme with DCM
    56
  - Multiplexed Clocking Scheme Without DCM
    56
  - Rxrecclk
    57
  - Clock Dependency
    57
  - Data Path Latency
    57
- Reset/Power down
  
  58
- 8B/10B Encoding/Decoding
  
  61
  - Overview
    61
    
    8B/10B Decoder
    61
    
    8B/10B Encoder
    61
  - Ports and Attributes
    62
    
    Txbypass8B10B, Rx_Decode_Use
    62
    
    Txchardispval, Txchardispmode
    63
    
    Rxcharisk, Rxrundisp
    64
    
    Txcharisk
    64
    
    Txkerr
    64
    
    Txrundisp
    64
    
    Rxdisperr
    65
    
    Rxnotintable
    65
  - Vitesse Disparity Example
    65
    
    Transmitting Vitesse Channel Bonding Sequence
    65
    
    Receiving Vitesse Channel Bonding Sequence
    66
  - 8B/10B Bypass Serial Output
    66
  - 8B/10B Serial Output Format
    67
  - HDL Code Examples: Transceiver Bypassing of 8B/10B Encoding
    67
- SERDES Alignment
  
  68
  - Overview
    68
    
    Deserializer
    68
    
    Serializer
    68
  - Ports and Attributes
    68
    
    Align_Comma_Msb
    68
    
    Enmcommaalign
    69
    
    Enpcommaalign
    69
    
    Enpcommaalign Enmcommaalign
    69
    
    Comma_10B_Mask, Pcomma_10B_Value, Mcomma_10B_Value
    71
    
    Dec_Mcomma_Detect Dec_Valid_Comma_Only
    71
    
    Mcomma_Detect
    71
    
    Pcomma_Detect
    71
    
    Rxrealign
    71
    
    Dec_Mcomma_Detect
    72
    
    Dec_Pcomma_Detect
    72
    
    Dec_Valid_Comma_Only
    72
    
    Rxchariscomma
    72
    
    Rxcommadet
    72
- Clock Recovery
  
  72
  - Overview
    72
    
    Clock and Data Recovery
    72
    
    Clock Synthesizer
    72
  - Clock Correction
    73
  - Ports and Attributes
    74
    
    Clk_Correct_Use
    74
    
    Rx_Buffer_Use
    74
    
    Clk_Cor_Keep_Idle Clk_Cor_Repeat_Wait
    75
    
    Clk_Cor_Seq_
    75
    
    Clk_Cor_Insert_Idle_Flag
    76
    
    Clk_Cor_Keep_Idle
    76
    
    Clk_Cor_Repeat_Wait
    76
- Synchronization Logic
  
  76
  - Overview
    76
  - Ports and Attributes
    77
    
    Rxclkcorcnt
    77
    
    Rx_Loss_Of_Sync_Fsm
    77
    
    Rx_Los_Invalid_Incr
    77
    
    Rx_Los_Threshold
    77
    
    Rxlossofsync
    78
- Channel Bonding (Channel Alignment)
  
  79
  - Overview
    79
  - Channel Bonding (Alignment) Operation
    80
  - Ports and Attributes
    81
    
    Chan_Bond_Mode
    81
    
    Chan_Bond_One_Shot
    81
    
    Chan_Bond_Seq_
    81
    
    Chan_Bond_Seq_2_Use
    81
    
    Chan_Bond__Seq_Len
    81
    
    Enchansync
    81
    
    Chan_Bond_Limit
    82
    
    Chan_Bond_Offset
    82
    
    Chan_Bond_Wait = 8
    82
    
    Chbonddone
    82
    
    Chbondi, Chbondo
    83
    
    Rxclkcorcnt, Rxlossofsync
    83
  - Troubleshooting
    83
- CRC (Cyclic Redundancy Check)
  
  83
  - Overview
    83
    
    CRC Operation
    83
    
    CRC Generation
    84
    
    CRC Latency
    84
  - Ports and Attributes
    85
    
    Crc_Format
    85
    
    Rx_Crc_Use
    85
    
    Tx_Crc_Use
    85
    
    Crc_End_Of_Packet
    88
    
    Crc_Start_Of_Packet
    88
    
    Rxcheckingcrc, Rxcrcerr
    88
    
    Txforcecrcerr, Tx_Crc_Force_Value
    88
  - Rocketio CRC Support Limitations
    88
- Fabric Interface (Buffers)
  
  89
  - Overview: Transmitter and Elastic (Receiver) Buffers
    89
    
    Receiver Buffer
    89
    
    Transmitter Buffer (FIFO)
    89
  - Ports and Attributes
    89
    
    Rxbufstatus
    89
    
    Txbuferr
    89
    
    Tx_Buffer_Use
    89
    
    Rx_Buffer_Use
    90
- Miscellaneous Signals
  
  90
  - Ports and Attributes
    90
    
    Serdes_10B
    90
    
    Termination_Imp
    90
    
    Tx_Data_Width
    90
    
    Loopback
    91
    
    Rxpolarity Txinhibit
    91
    
    Tx_Diff_Ctrl Pre_Emphasis
    91
- Other Important Design Notes
  
  92
- Other Important Design Notes
  
  93
  - Bit Alignment Design
    94
    
    Verilog
    94
    
    Vhdl
    97
Chapter 3 : Analog Design Considerations

101
- Serial I/O Description
  
  101
- Pre-Emphasis Techniques
  
  102
- Differential Receiver
  
  105
- Jitter
  
  105
  - Clock and Data Recovery
    106
- PCB Design Requirements
  
  107
  - Power Conditioning
    107
    
    Voltage Regulation
    107
    
    Passive Filtering
    109
  - High-Speed Serial Trace Design
    112
    
    Routing Serial Traces
    112
    
    Differential Trace Design
    113
    
    AC and DC Coupling
    114
  - Reference Clock
    116
    
    Epson EG-2121CA 2.5V (LVPECL Outputs)
    116
    
    Pletronics LV1145B (LVDS Outputs)
    116
  - Powering the Rocketio Transceivers
    117
  - Other Important Design Notes
    117
  - The POWERDOWN Port
    117

Xilinx Categories

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More Xilinx Manuals

Xilinx RocketIO Manuals

Xilinx RocketIO User Manual (204 pages)

Table of Contents

Chapter 1: Rocketio X Transceiver Overview

Chapter 3: Clocking and Clock Domains

Chapter 2: Digital Design Considerations

Chapter 4: Analog Design Considerations

Chapter 5: Simulation and Implementation

Appendix A: Rocketio X Transceiver Timing Model

Appendix A: Rocketio X Transceiver Timing Model

Appendix B: 8B/10B Valid Characters

Appendix C: PMA Attribute Programming Bus

Appendix C: PMA Attribute Programming Bus

Xilinx RocketIO User Manual (156 pages)

Table of Contents

Schedule of Figures

Schedule of Tables

Preface: about this Guide

Rocketio Features

Guide Contents

For more Information

Additional Resources

Conventions

Chapter 1 : Rocketio Transceiver Overview

Basic Architecture and Capabilities

Rocketio Transceiver Instantiations

List of Available Ports

Primitive Attributes

Modifiable Primitives

Byte Mapping

Chapter 2: Digital Design Considerations

Clocking

Reset/Power down

8B/10B Encoding/Decoding

SERDES Alignment

Clock Recovery

Synchronization Logic

Channel Bonding (Channel Alignment)

CRC (Cyclic Redundancy Check)

Fabric Interface (Buffers)

Miscellaneous Signals

Other Important Design Notes

Chapter 3 : Analog Design Considerations

Serial I/O Description

Pre-Emphasis Techniques

Differential Receiver

Jitter

PCB Design Requirements

Other Important Design Notes

Chapter 4 : Simulation and Implementation

Simulation Models

Implementation Tools

MGT Package Pins

Xilinx RocketIO User Manual (124 pages)

Table of Contents

Chapter 1: Introduction

Chapter 2: Rocketio Transceiver Overview

Chapter 3: Digital Design Considerations

Chapter 4 : Analog Design Considerations

Chapter 5: Simulation and Implementation

Xilinx RocketIO User Manual (152 pages)

Table of Contents

Schedule of Figures

Schedule of Tables

Preface: about this Guide

Rocketio Features

Guide Contents

For more Information

Additional Resources

Conventions

Chapter 1 : Rocketio Transceiver Overview

Basic Architecture and Capabilities

Rocketio Transceiver Instantiations

List of Available Ports

Primitive Attributes

Modifiable Primitives

Byte Mapping

Chapter 2: Digital Design Considerations

Clocking

Reset/Power down