Xilinx 7 Series User Manual page 104

Chapter 3: Transmitter
Table 3-19: PCI Express Compliance Pattern
X-Ref Target - Figure 3-16
The error insertion function is supported to verify link connection and also for jitter tolerance tests.
When an inverted PRBS pattern is necessary, the TXPOLARITY signal is used to control polarity.
Figure 3-17
X-Ref Target - Figure 3-17
PCI Express Compliance Pattern
Ports and Attributes
Table 3-20
104
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Symbol K28.5
Disparity 0
Pattern
0011111010
Figure 3-16: 20-UI Square Wave
shows the TX pattern generator block.
PRBS-7
PRBS-15
PRBS-23
PRBS-31
Square Wave with 2 UI period
Square Wave with
16 UI or 20 UI period
TXDATA
Figure 3-17: TX Pattern Generator Block
defines the pattern generator ports.
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D21.5 K28.5
1 1
1010101010 1100000101
20 UI
Error
Insertions
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
D10.2
0
0101010101
UG482_c3_15_110911
Polarity
Inversion
UG482_c3_16_110911