Xilinx 7 Series User Manual page 36

Chapter 2: Shared Features
Table 2-7
Table 2-7: PLL Divider Settings
Ports and Attributes
Table 2-8
Table 2-8: PLL Ports
Port
PLL0LOCKDETCLK
PLL1LOCKDETCLK
PLL0LOCKEN
PLL1LOCKEN
PLL0PD
PLL1PD
BGBYPASSB
BGMONITORENB
BGPDB
BGRCALOVRD[4:0]
RCALENB
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lists the allowable divider settings.
Factor Attribute
M PLL0_REFCLK_DIV
PLL1_REFCLK_DIV
N2 PLL0_FBDIV
PLL1_FBDIV
N1 PLL0_FBDIV_45
PLL1_FBDIV_45
D RXOUT_DIV
TXOUT_DIV
and Table 2-9 defines the ports and attributes for the PLL.
Direction Clock Domain
In Clock
In Async
In Async
In Async
In Async
In Async
In Async
In Async
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Valid Settings
1, 2
1, 2, 3, 4, 5
4, 5
1, 2, 4, 8
Description
Stable reference clock for the detection of the feedback and
reference clock signals to the PLL. The input reference
clock to the PLL or any output clock generated from the
PLL (e.g., TXOUTCLK) must not be used to drive this
clock.
This clock is required only when using the
PLL[0/1]FBCLKLOST and PLL[0/1]REFCLKLOST
ports. It does not affect the PLL lock detection, reset, and
power-down functions.
This port enables the PLL lock detector. It must always be
tied High.
Active-High signal that powers down the PLL for power
savings.
Reserved. This port must be set to 1'b1. This value should
not be modified.
Reserved. This port must be set to 1'b1. This value should
not be modified.
Reserved. This port must be set to 1'b1. This value should
not be modified.
Reserved. This port must be set to 5'b111111. This value
should not be modified.
Reserved. This port must be set to 1'b1. This value should
not be modified.
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016