Rx Polarity Control - Xilinx 7 Series User Manual

Table 4-20: RX Margin Analysis Attributes (Cont'd)
Attribute
RXOUT_DIV Integer
USE_PCS_CLK_PHASE
_SEL Binary
ES_CLK_PHASE_SEL
Binary
Table 4-21: DRP Address Map for Eye Scan Read-Only (R) Registers

RX Polarity Control

Functional Description
If RXP and RXN differential traces are accidentally swapped on the PCB, the differential data
received by the GTP transceiver RX are reversed. The GTP transceiver RX allows inversion to be
done on parallel bytes in the PCS after the SIPO to offset reversed polarity on differential pair.
Polarity control function uses the RXPOLARITY input, which is driven High from the fabric user
interface to invert the polarity.
Ports and Attributes
Table 4-22
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
Type
PLL0 or PLL1 output clock divider D for the RX datapath as shown in
Valid settings are 1, 2, 4, or 8.
This attribute sets the divider only if the RXRATE port is set to 3'b000.
1-bit If set to 1, Eye Scan 4T clock phase is determined by ES_CLK_PHASE_SEL.
If set to 0, deserializer phase detector determines phase of Eye Scan 4T clock.
1-bit If USE_PCS_CLK_PHASE_SEL is asserted, setting to 1 selects one phase of Eye Scan 4T clock.
Setting to 0 selects the other phase.
DRP Address
DRP Bits
Hex
151 15:0
152 15:0
153 3:0
154 15:0
155 15:0
156 15:0
157 15:0
158 15:0
159 15:0
15A 15:0
15B 15:0
15C 15:0
15D 15:0
defines the ports required by the RX polarity control function.
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Description
R/W Name
R es_error_count
R es_sample_count
R es_control_status
R es_rdata
R es_rdata
R es_rdata
R es_rdata
R es_rdata
R es_sdata
R es_sdata
R es_sdata
R es_sdata
R es_sdata
Send Feedback
RX Polarity Control
Figure 2-9, page 35.
Attribute Bit
15:0
15:0
3:0
79:64
63:48
47:32
31:16
15:0
79:64
63:48
47:32
31:16
15:0
157