Xilinx 7 Series User Manual page 306

Appendix D: DRP Address Map of the GTP Transceiver
Table D-2: DRP Map of GTPE2_CHANNEL Primitive (Cont'd)
DRP
DRP Bits
Address
0
009D
2
009E
1
009E
0
009E
8:0
009F
8:0
00A0
15:0
00A1
7:0
00A2
15:0
00A3
7:0
00A4
13:0
00A5
9:0
00A6
13
00A7
12
00A7
11
00A7
5:0
00A7
15:0
00A8
15:0
00A9
15:0
00AA
15:0
00AB
15:0
00AC
2:0
00AD
306
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R/W Attribute Name
R/W RX_DEFER_RESET_BUF_EN
R/W RXBUF_RESET_ON_COMMAALIGN
R/W RXBUF_RESET_ON_RATE_CHANGE
R/W RXBUF_RESET_ON_CB_CHANGE
R/W TXDLY_LCFG
R/W RXDLY_LCFG
R/W RXPH_CFG
R/W RXPH_CFG
R/W RXPHDLY_CFG
R/W RXPHDLY_CFG
R/W RX_DEBUG_CFG
R/W ES_PMA_CFG
R/W RXCDR_PH_RESET_ON_EIDLE
R/W RXCDR_FR_RESET_ON_EIDLE
R/W RXCDR_HOLD_DURING_EIDLE
R/W RXCDR_LOCK_CFG
R/W RXCDR_CFG
R/W RXCDR_CFG
R/W RXCDR_CFG
R/W RXCDR_CFG
R/W RXCDR_CFG
R/W RXCDR_CFG
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Attribute Attribute
Bits Encoding
FALSE
0
TRUE
FALSE
0
TRUE
FALSE
0
TRUE
FALSE
0
TRUE
8:0 0-511
8:0 0-511
15:0 0-65535
23:16 0-255
15:0 0-65535
23:16 0-255
13:0 0-16383
9:0 0-1023
0 0-1
0 0-1
0 0-1
5:0 0-63
15:0 0-65535
31:16 0-65535
47:32 0-65535
63:48 0-65535
79:64 0-65535
82:80 0-7
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
DRP
Encoding
0
1
0
1
0
1
0
1
0-511
0-511
0-65535
0-255
0-65535
0-255
0-16383
0-1023
0-1
0-1
0-1
0-63
0-65535
0-65535
0-65535
0-65535
0-65535
0-7