Xilinx 7 Series User Manual page 49

X-Ref Target - Figure 2-18
EYESCANRESET
Ports and Attributes
Table 2-18
Table 2-18: RX Initialization and Reset Ports
GTRXRESET
RXOSCALRESET
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
RXPMARESET
WAIT until
High
RXPMARESET
from High to Low
RXLPMRESET
WAIT until
High
RXLPMRESET
from High to Low
WAIT until
High
EYESCANRESET
from High to Low
RXPCSRESET
WAIT until
High
RXPCSRESET
from High to Low
RXBUFRESET
WAIT until
High
RXBUFRESET
from High to Low
Figure 2-18: GTP Transceiver RX Reset State Machine Sequence
lists the ports required by the GTP transceiver's RX initialization process.
Port Dir
In
In
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GTRXRESET
High
WAIT until
GTRXRESET
from High to Low
RXPMARESET
Process
RXLPMRESET
Process
EYESCANRESET
Process
Sequence Mode & RXUSERRDY
RXPCSRESET
Process
RXBUFRESET
Process
RXRESETDONE
High
Clock Domain
Async This port is driven High and then deasserted to
start the full Channel RX reset sequence.
Async Reserved. The recommended value from the 7
Series FPGAs Transceivers Wizard should be
used.
Reset and Initialization
Single
RXPMARESET Done
Mode
when
RXRESETDONE High
Single
RXLPMRESET
Mode
Done when
RXRESETDONE High
Single
EYESCANRESET
Mode
Done when
RXRESETDONE High
RXPCSRESET Done
when
Single
RXRESETDONE High
Mode
RXBUFRESET Done
when
Single
RXRESETDONE High
Mode
UG482_c2_118_021113
Description
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