Xilinx 7 Series User Manual page 292

Appendix D: DRP Address Map of the GTP Transceiver
Table D-2: DRP Map of GTPE2_CHANNEL Primitive (Cont'd)
DRP
DRP Bits
Address
0045
15:10
(Cont'd)
9:0
0045
15:10
0046
292
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R/W Attribute Name
R/W CLK_COR_MAX_LAT
R/W CLK_COR_SEQ_1_2
R/W CLK_COR_MIN_LAT
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Attribute Attribute
Bits Encoding
40
41
42
43
44
45
46
47
48
49
5:0 50
51
52
53
54
55
56
57
58
59
60
9:0 0-1023
4
5
6
7
5:0 8
9
10
11
12
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
DRP
Encoding
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
0-1023
4
5
6
7
8
9
10
11
12