Xilinx 7 Series User Manual page 58

Chapter 2: Shared Features
Table 2-21: RX Component Reset Coverage in Single Mode
RX PMA
Table 2-22
Table 2-22: Recommended Resets for Common Situations
Situation
After power up and configuration
After turning on a reference clock to the PLL
being used
After changing the reference clock to the PLL
being used
After assertion/deassertion of
PLL[0/1]PD, for the PLL being used
After assertion/deassertion of RXPD[1:0]
RX rate change
RX parallel clock source reset
58
Send Feedback
Functional Blocks
FPGA RX Fabric
Interface
RX Gearbox
RX Status Control
RX Delay Aligner
RX 8B/10B Encoder
RX PCS
RX Comma Detect and
Alignment
RX Polarity
PRBS Checker
RX Elastic Buffer
RX Reset FSM
RX Analog Front End
RX Out-of-Band
Signaling
RX SIPO
RX CDR Phase Path
RX CDR Frequency
Path
RX LPM
RX ISCAN
lists the recommended resets for various situations.
Components to
be Reset
Entire RX
Entire RX
Entire RX
Entire RX
Entire RX
Entire RX
RX PCS
www.xilinx.com
GTRX RXPMA RXLPM EYESCAN
RESET RESET RESET
√
√
√
√
Recommended Reset
GTRXRESET
GTRXRESET
GTRXRESET
GTRXRESET
GTRXRESET
GTRXRESET or reset sequence is performed
automatically due to RXRATE
RXPCSRESET
7 Series FPGAs GTP Transceivers User Guide
RXPCS RXBUF
RESET RESET RESET
√
√
√
√
√
√
√
√
√
√
(1)
UG482 (v1.9) December 19, 2016
RXOOB
RESET
√