Xilinx 7 Series User Manual page 181

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Figure 4-39
X-Ref Target - Figure 4-39
M_RXPHDLYRESET
M_RXDLYBYPASS
M_RXPHALIGNEN
M_RXDDIEN
M_RXDLYSRESET
M_RXDLYSRESETDONE
M_RXPHALIGN
M_RXDLYEN
M_RXPHALIGNDONE
S_RXPHDLYRESET
S_RXDLYBYPASS
S_RXPHALIGNEN
S_RXDDIEN
S_RXDLYSRESET
S_RXDLYSRESETDONE
S_RXPHALIGN
S_RXDLYEN
S_RXPHALIGNDONE
Figure 4-39: RX Phase and Delay Alignment in Manual Mode
Notes relevant to
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10. Deassert RXPHALIGN for the master lane.
11. Assert RXDLYEN for the master lane. This causes RXPHALIGNDONE to be deasserted.
12. Hold RXDLYEN for the master lane High until the rising edge of RXPHALIGNDONE of the
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
Resetting or powering up the PLL
Changing the RX recovered clock source or frequency
Changing the GTP transceiver RX line rate
shows the required steps to perform manual RX phase and delay alignment.
Figure 4-39:
The sequence of events shown in
M_* denotes ports related to the master lane.
S_* denotes ports related to the slave lane(s).
Set the RXSYNC_OVRD attribute to 1'b1.
Set RXPHDLYRESET and RXDLYBYPASS to Low for all lanes.
Set RXPHALIGNEN and RXDDIEN to High for all lanes.
Assert RXDLYSRESET for all lanes. Hold this signal High until RXDLYSRESETDONE of
the respective lane is asserted.
Deassert RXDLYSRESET for the lane in which the RXDLYSRESETDONE is asserted.
When RXDLYSRESET of all lanes are deasserted, assert RXPHALIGN for the master lane.
Hold this signal High until the rising edge of RXPHALIGNDONE of the master lane is
observed.
master lane is observed.
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Figure 4-39 is not drawn to scale.
RX Buffer Bypass
UG482_c4_39_020713
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