Xilinx 7 Series User Manual page 268

Appendix D: DRP Address Map of the GTP Transceiver
Table D-2: DRP Map of GTPE2_CHANNEL Primitive (Cont'd)
DRP
DRP Bits
Address
0011
10:6
(Cont'd)
5:4
0011
0
0011
15:12
0012
11:10
0012
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R/W Attribute Name
R/W RX_CLK25_DIV
R/W RX_CM_SEL
R/W RXPRBS_ERR_LOOPBACK
R/W SATA_BURST_SEQ_LEN
R/W OUTREFCLK_SEL_INV
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Attribute Attribute
Bits Encoding
5
6
7
8
9
10
11
12
13
14
15
16
17
18
4:0
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1:0 0-3
0 0-1
3:0 0-15
1:0 0-3
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
DRP
Encoding
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0-3
0-1
0-15
0-3