Chapter 2: Shared Transceiver Features; Reference Clock Input Structure; Functional Description - Xilinx Virtex-6 FPGA User Manual

Shared Transceiver Features

Reference Clock Input Structure

Functional Description

The reference clock input structure is illustrated in
internally with 50Ω on each leg to 2/3 MGTHAVCCPLL. The reference clock input is
instantiated in software with an IBUFDS_GTHE1 primitive. Its location is fixed via LOC
constraints in the UCF. Refer to
The output of the IBUFDS_GTHE1 primitive drives the REFCLK input of the
GTHE1_QUAD primitive. The ports and attributes controlling each of the
IBUFDS_GTHE1 primitives are mapped to the respective GTHE1_QUAD primitive.
X-Ref Target - Figure 2-1
MGTHAVCCPLL_[L,R]
MGTHAVCCRX_[L,R]
MGTREFCLKP
MGTREFCLKN
Virtex-6 FPGA GTH Transceivers User Guide
UG371 (v2.0) February 16, 2010
pll_refclk_term_b
Nominal 50Ω
Nominal 50Ω
Figure 2-1: Reference Clock Input Structure
www.xilinx.com
Figure
Implementation, page 31
2/3
MGTHAVCCPLL_[L,R]
Chapter 2
2-1. The input is terminated
for details.
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