Xilinx 7 Series User Manual page 144

Chapter 4: Receiver
Table 4-12: CDR Attributes (Cont'd)
RXCDR_PH_RESET_ON_EIDLE
RX_OS_CFG[12:0]
Use Modes
RX CDR Lock to Reference
To get the CDR to lock to reference set RXCDRHOLD = 1'b1 and set RXCDROVRDEN = 1'b0
Dynamically Changing RX CDR Settings for Line Rate and Selected Protocol
Changes
The sequence of events to dynamically change the RX CDR settings is described here. It pertains
only to changes for the CDR:
1.
2.
3.
4.
5.
Dynamically Changing RX CDR Settings to Tune CDR Loop Filter Settings
Only
1.
2.
After the RXRESETDONE signal goes High, correct data must be verified before continuing with
the operation of the transceiver (i.e., check a known data pattern).
Table 4-13: CDR Recommended Settings for Scrambled/PRBS Data
144
Send Feedback
Attribute
When ready (i.e., all valid data is flushed out of the receiver datapath), use the DRP to
implement changes to the CDR loop filter settings with the attribute RXCDR_CFG[83:0].
Recommended settings for this attribute are provided in
Provide the changes via ports PLL[0/1]REFCLKSEL and/or the DRP to the attributes listed in
Table 2-9, page 35.
Follow the reset guidelines as detailed in
When the PLL has locked, assert GTRXRESET and follow the guidelines detailed in
Transceiver TX Reset in Response to GTTXRESET Pulse, page
After the RXRESETDONE signal goes High, correct data must be verified before continuing
with the operation of the transceiver (i.e., check a known data pattern).
When ready (all valid data flushed out of receiver datapath), use the DRP to implement changes
to the CDR loop filter settings with the attribute RXCDR_CFG[83:0]. Recommended settings
for this attribute are provided in
Assert the GTRXRESET port and follow the guidelines detailed in
in Response to GTRXRESET Pulse, page
RXOUT_DIV REFCLK PPM
±200
1 ±700
±1,250
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Type
Binary Enables automatic reset of the CDR phase
during the optional PCI Express reset
sequence during electrical idle.
13-bit Binary Reserved. The recommended value from
the 7 Series FPGAs Transceivers Wizard
should be used.
Table
PLL Reset, page 41.
Table 4-13, Table 4-14, and Table
54.
RXCDR_CFG
83'h0_0011_07FE_2060_2104_1010
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
Description
4-13, Table 4-14, and Table 4-15.
GTP
44.
4-15.
GTP Transceiver RX Reset
(1) (2)
(No SSC )