Xilinx 7 Series User Manual page 13

X-Ref Target - Figure 1-1
Artix-7 FPGA (XC7A100T)
I/O CMT
Column Column
Figure 1-1: GTP Transceiver Inside Artix-7 XC7A100T FPGA
Additional information on the functional blocks of 7 series FPGAs is available at:
Figure 1-2
GTPE2_COMMON primitive to form a Quad.
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
Integrated
Block for PCI
Express
Operation
Configuration
UG470 , 7 Series FPGAs Configuration User Guide provides more information on the
configuration.
UG471, 7 Series FPGAs SelectIO Resources User Guide provides more information on the I/O
blocks.
UG472, 7 Series FPGAs Clocking Resources User Guide provides more information on the
mixed mode clock manager (MMCM).
illustrates the clustering of four GTPE2_CHANNEL primitives and one
www.xilinx.com
Overview and Features
GTP Quad
GTPE2_CHANNEL_X0Y7
GTPE2_CHANNEL_X0Y6
GTPE2_
COMMON_
X0Y1
GTPE2_CHANNEL_X0Y5
GTPE2_CHANNEL_X0Y4
CMT
Column
GTP Quad
GTPE2_CHANNEL_X0Y3
GTPE2_CHANNEL_X0Y2
GTPE2_
COMMON_
X0Y0
GTPE2_CHANNEL_X0Y1
GTPE2_CHANNEL_X0Y0
Send Feedback
I/O
Column
UG482_C1_01_110811
13