Xilinx 7 Series User Manual page 94

Chapter 3: Transmitter
Table 3-12: TX Buffering versus Phase Alignment
Ease of Use
Latency
TX Lane-to-Lane
Deskew
Ports and Attributes
Table 3-13
Table 3-13: TX Buffer Ports
TXBUFSTATUS[1:0]
Table 3-14
Table 3-14: TX Buffer Attributes
TXBUF_EN
94
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TX Buffer
The TX buffer is the
recommended default
to use when possible. It
is robust and easier to
operate.
If low latency is critical,
the TX buffer must be
bypassed.
defines the TX buffer ports.
Port Dir Clock Domain
Out TXUSRCLK2
defines the TX buffer attributes.
Attribute
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TX Phase Alignment
Phase alignment is an advanced feature that
requires extra logic and additional constraints on
clock sources. TXOUTCLKSEL must select the
GTP transceiver reference clock as the source of
TXOUTCLK to drive TXUSRCLK.
Phase alignment uses fewer register in the TX
datapath to achieve lower and deterministic latency.
The TX phase alignment circuit can be used to
reduce the lane skew between separate GTP
transceivers. All GTP transceivers involved must
use the same line rate.
Description
TX buffer status.
TXBUFSTATUS[1]: TX buffer overflow or
underflow status. When TXBUFSTATUS[1] is
set High, it remains High until the TX buffer is
reset.
1: TX FIFO has overflow or underflow.
0: No TX FIFO overflow or underflow error.
TXBUFSTATUS[0]: TX buffer fullness.
1: TX FIFO is at least half full.
0: TX FIFO is less than half full.
Type Description
String Use or bypass the TX buffer.
TRUE: Uses the TX buffer (default).
FALSE: Bypasses the TX buffer
(advanced feature).
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016