Xilinx 7 Series User Manual page 100

Chapter 3: Transmitter
X-Ref Target - Figure 3-13
Skew
Figure 3-13: TX Phase Alignment to Minimize TX Lane-to-Lane Skew
Using TX Buffer Bypass in Multi-Lane Mode
This section describes the steps required to perform the multi-lane TX buffer bypass alignment
procedure.
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GTP TX
Lane 0
Parallel clocks
are independent
GTP TX
Lane 1
Before TX Phase Alignment
Master: In a multi-lane application, the buffer bypass master is the lane that is the source of
TXOUTCLK.
Slave: All the lanes that share the same TXUSRCLK/TXUSRCLK2, which is generated from
the TXOUTCLK of the buffer bypass master.
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GTP TX
Lane 0
Reduced Skew
Parallel clocks are
phase aligned to the
same clock edge
GTP TX
Lane 1
After TX Phase Alignment
UG482_c3_114_020413
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016