Xilinx 7 Series User Manual page 142

Chapter 4: Receiver
Ports and Attributes
Table 4-11
Table 4-11: CDR Ports
Port
RXCDRFREQRESET
RXCDRHOLD
RXCDROVRDEN
RXCDRRESET
RXCDRRESETRSV
RXRATE[2:0]
RXCDRLOCK
RXOSHOLD
RXOSOVRDEN
RXOSCALRESET
RXOSINTPD
RXOSINTCFG[3:0]
RXOSINTD0[3:0]
RXOSINTOVRDEN
142
Send Feedback
defines the CDR ports.
Dir Clock Domain
In Async
In Async
In Async
In Async
In Async
In RXUSRCLK2
(RXRATEMODE
makes this port
asynchronous)
Out Async
In Async
In Async
In Async
In Async
In Async
In Async
In Async
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Description
Reserved. Tied Low.
Hold the CDR control loop frozen.
Reserved.
Reserved. Tied Low.
Reserved.
This port dynamically controls the setting for the
RX serial clock divider D (see
is used with RXOUT_DIV attribute.
3'b000: Use RXOUT_DIV divider value
3'b001: Set D divider to 1
3'b010: Set D divider to 2
3'b011: Set D divider to 4
3'b100: Set D divider to 8
RXBUF_RESET_ON_RATE_CHANGE
attribute enable optional automatic reset.
Reserved.
When set to 1'b1, the current value of the offset
cancellation is held.
When set to 1'b0, the offset cancellation is
adapted.
When set to 1'b1, the Offset Cancellation is
controlled by the RX_OS_CFG attribute.
When set to 1'b0, the AGC is controlled by the
RXOSHOLD signal.
Reserved. The recommended value from the 7
Series FPGAs Transceivers Wizard should be
used.
Reserved. The recommended value from the 7
Series FPGAs Transceivers Wizard should be
used.
Reserved. The recommended value from the 7
Series FPGAs Transceivers Wizard should be
used..
Reserved. The recommended value from the 7
Series FPGAs Transceivers Wizard should be
used.
Reserved. The recommended value from the 7
Series FPGAs Transceivers Wizard should be
used.
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
Table 4-16) and it