Xilinx 7 Series User Manual page 265

DRP Address Map of the GTP Transceiver
Table D-1
Note:
automatically by the 7 Series FPGAs Transceivers Wizard. These attributes must be left at their
defaults, except for use cases that explicitly request different values.
Table D-1: DRP Map of GTPE2_COMMON Primitive
DRP Address
DRP Bits
(Hex)
15:0
0002
10:0
0003
13:9
0004
7
0004
5.0
0004
8:0
0005
15:0
0006
7:0
0007
15:0
000A
1
000F
0
000F
15:0
0011
15:0
0012
7:0
0013
15:0
0019
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
lists the DRP map of the GTPE2_COMMON primitive sorted by address.
The reserved bits should NOT be modified. Attributes that are not described explicitly are set
R/W Attribute Name
R/W PLL0_CFG
R/W PLL0_CFG
R/W PLL0_REFCLK_DIV
R/W PLL0_FBDIV_45
R/W PLL0_FBDIV
R/W PLL0_LOCK_CFG
R/W PLL0_INIT_CFG
R/W PLL0_INIT_CFG
R/W RSVD_ATTR0
R/W PLL1_DMON_CFG
R/W PLL0_DMON_CFG
R/W COMMON_CFG
R/W COMMON_CFG
R/W PLL_CLKOUT_CFG
R/W BIAS_CFG
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Appendix D
Attribute Attribute DRP Binary
Bits Encoding Encoding
15:0 0–65535
26:16 0–2047
1
4:0
2
4
0
5
1
2
5:0 3
4
5
8:0 0-511
15:0 0-65535
23:16 0-255
15:0 0-65535
0 0-1
0 0-1
15:0 0-65535
31:16 0-65535
7:0 0-255
15:0 0-65535
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0–65535
0–2047
16
0
0
1
16
0
1
2
3
0-511
0-65535
0-255
0-65535
0-1
0-1
0-65535
0-65535
0-255
0-65535
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