Xilinx 7 Series User Manual page 26

Chapter 2: Shared Features
X-Ref Target - Figure 2-2
GTP Quad
To GTPE2_CHANNEL
PLL0 PLL1
1 2 3 4 5 6 7 1 2 3 4 5 6 7
IBUFDS_GTE2 IBUFDS_GTE2
Figure 2-2: Conceptual View of GTP Transceiver Reference Clocking
Figure 2-3
single GTPE2_COMMON primitive. The PLL0REFCLKSEL and PLL1REFCLKSEL ports are
required when multiple reference clock sources are connected to the multiplexers. A single
reference clock is most commonly used. In this case, the PLL[0/1]REFCLKSEL port can be tied to
3'b001, and the Xilinx software tools handle the complexity of the multiplexers and associated
routing. See
26
Send Feedback
GTPE2_
COMMON_
X0Y0
Controlled by Software
GTEASTREFCLK0
GTEASTREFCLK1
shows the shows the detailed view of the reference clock multiplexer structures within a
External Reference Clock Use Model, page 31
www.xilinx.com
GTP Quad
To GTPE2_CHANNEL
GTPE2_
COMMON_
PLL0
X1Y0
1 2 3 4 5 6 7
Controlled by Software
GTWESTREFCLK1
GTWESTREFCLK0
IBUFDS_GTE2 IBUFDS_GTE2
for more information.
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
PLL1
1 2 3 4 5 6 7
UG482_c2_01_012413