Xilinx 7 Series User Manual page 301

Table D-2: DRP Map of GTPE2_CHANNEL Primitive (Cont'd)
DRP
DRP Bits
Address
14
008E
13
008E
12:9
008E
8:0
008E
7:5
008F
4
008F
3
008F
2:0
008F
15
0091
14
0091
12:6
0091
15:0
0092
3:0
0093
7:0
0095
5
0096
4
0096
3
0096
2:0
0096
15:0
0097
15:0
0098
15:0
0099
15:0
009A
5:0
009B
8
009C
6
009C
5:0
009C
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
R/W Attribute Name
R/W RXLPM_INCM_CFG
R/W CFOK_CFG4
R/W CFOK_CFG6
R/W RXLPM_GC_CFG
R/W RXLPM_GC_CFG2
R/W RXPI_CFG1
R/W RXPI_CFG2
R/W RXLPM_OSINT_CFG
R/W ES_CLK_PHASE_SEL
R/W USE_PCS_CLK_PHASE_SEL
R/W CFOK_CFG2
R/W ADAPT_CFG0
R/W ADAPT_CFG0
R/W TXPI_PPM_CFG
R/W TXPI_GREY_SEL
R/W TXPI_INVSTROBE_SEL
R/W TXPI_PPMCLK_SEL
R/W TXPI_SYNFREQ_PPM
R/W TST_RSV
R/W TST_RSV
R/W PMA_RSV
R/W PMA_RSV
R/W RX_BUFFER_CFG
R/W RXBUF_THRESH_OVRD
R/W RXBUF_RESET_ON_EIDLE
R/W RXBUF_THRESH_UNDFLW
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Attribute Attribute
Bits Encoding
0 0-1
0 0-1
3:0 0-15
8:0 0-511
2:0 0-7
0 0-1
0 0-1
2:0 0-7
0 0-1
0 0-1
6:0 0-127
15:0 0-65535
19:16 0-15
7:0 0-255
0 0-1
0 0-1
TXUSRCLK
0
TXUSRCLK2
2:0 0-7
15:0 0-65535
31:16 0-65535
15:0 0-65535
31:16 0-65535
5:0 0-63
FALSE
0
TRUE
FALSE
0
TRUE
0
1
5:0
2
3
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DRP
Encoding
0-1
0-1
0-15
0-511
0-7
0-1
0-1
0-7
0-1
0-1
0-127
0-65535
0-15
0-255
0-1
0-1
0
1
0-7
0-65535
0-65535
0-65535
0-65535
0-63
0
1
0
1
0
1
2
3
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