Xilinx 7 Series User Manual page 293

Table D-2: DRP Map of GTPE2_CHANNEL Primitive (Cont'd)
DRP
DRP Bits
Address
0046
15:10
(Cont'd)
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
R/W Attribute Name
R/W CLK_COR_MIN_LAT
www.xilinx.com
Attribute Attribute
Bits Encoding
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
5:0
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Send Feedback
DRP
Encoding
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
293