Xilinx 7 Series User Manual page 159

Ports and Attributes
Table 4-23
Table 4-23: Pattern Checker Ports
RXPRBSCNTRESET
RXPRBSSEL[2:0]
RXPRBSERR
Table 4-24
Table 4-24: Pattern Checker Attributes
RX_PRBS_ERR_CNT
RXPRBS_ERR_LOOPBACK
Use Models
To use the built-in PRBS checker, RXPRBSSEL must be set to match the PRBS pattern being sent
to the receiver. The RXPRBSSEL entry in
checker is running, it attempts to find the selected PRBS pattern in the incoming data. If the
incoming data is inverted by the transmitter or reversed RXP/RXN, the received data should also
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
defines the pattern checker ports.
Port Dir Clock Domain
In RXUSRCLK2
In RXUSRCLK2
Out RXUSRCLK2
defines the pattern checker attributes.
Attribute
16-bit Binary
1-bit Binary
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Resets the PRBS error counter.
Receiver PRBS checker test pattern control.
Only these settings are valid:
000: Standard operation mode. (PRBS
check is off)
001: PRBS-7
010: PRBS-15
011: PRBS- 23
100: PRBS-31
No checking is done for non-PRBS patterns.
Single bit errors cause bursts of PRBS errors
because the PRBS checker uses data from the
current cycle to generate next cycle's
expected data.
This non-sticky status output indicates that
PRBS errors have occurred.
Type
PRBS error counter. This counter can be reset
by asserting RXPRBSCNTRESET. When an
error(s) in incoming parallel data occurs, this
counter increments by 1 and counts up to
0xFFFF. This error counter can only be
accessed via the DRP. The address for this
counter is 0x15E.
When this attribute is set to 1, the
RXPRBSERR bit is internally looped back to
TXPRBSFORCEERR of the same GTP
transceiver. This allows synchronous and
asynchronous jitter tolerance testing without
worrying about data clock domain crossing.
When this attribute is set to 0,
TXPRBSFORCEERR is forced onto the TX
PRBS.
Table 4-23 shows the available settings. When the PRBS
RX Pattern Checker
Description
Description
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