Xilinx 7 Series User Manual page 31

Table 2-6: GTPE2_CHANNEL Clocking Ports
RXSYSCLKSEL[1:0]
TXSYSCLKSEL[1:0]
PLL0CLK
PLL1CLK
PLL0REFCLK
PLL1REFCLK
External Reference Clock Use Model
Each Quad has two dedicated differential reference clock inputs that can be connected to external
reference clock sources. An IBUFDS_GTE2 primitive must be instantiated to use these dedicated
reference clock pin pairs. The user design connects the IBUFDS_GTE2 output (O) to the
GTREFCLK[0/1], GTEASTREFCLK[0/1] or GTWESTREFCLK[0/1] ports of the
GTPE2_COMMON primitive where the reference clock selection multiplexer is located.
Depending on the line rate requirement, the user design has the flexibility to use different
combinations of PLL0 or PLL1 to drive the TX and/or RX datapath, as shown in
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
Port
Direction
In
In
In
In
In
In
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Reference Clock Selection and Distribution
Clock
Description
Domain
Async Selects the PLL clock source to drive the RX
datapath:
RXSYSCLKSEL[0] = 1'b0 (PLL0)
RXSYSCLKSEL[0] = 1'b1 (PLL1)
Selects the reference clock source to drive
RXOUTCLK:
RXSYSCLKSEL[1] = 1'b0 (reference
clock from PLL0)
RXSYSCLKSEL[1] = 1'b1 (reference
clock from PLL1)
Async Selects the PLL clock source to drive the TX
datapath:
TXSYSCLKSEL[0] = 1'b0 (PLL0)
TXSYSCLKSEL[0] = 1'b1 (PLL1)
Selects the reference clock source to drive
TXOUTCLK:
TXSYSCLKSEL[1] = 1'b0 (reference
clock from PLL0)
TXSYSCLKSEL[1] = 1'b1 (reference
clock form PLL1)
Clock PLL0 clock input. The user must connect this
port to the PLL0OUTCLK port on the
GTPE2_COMMON primitive.
Clock PLL1 clock input. The user must connect this
port to the PLL1OUTCLK port on the
GTPE2_COMMON primitive.
Clock The user must connect this port to the
PLL0OUTREFCLK port on the
GTPE2_COMMON primitive.
Clock The user must connect this port to the
PLL1OUTREFCLK port on the
GTPE2_COMMON primitive.
Figure 2-4.
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