Rx Margin Analysis - Xilinx 7 Series User Manual

Chapter 4: Receiver
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RX Margin Analysis

Functional Description
As line rates and channel attenuation increase, the receiver equalizers are more often enabled to
overcome channel attenuation. This poses a challenge to system bring-up because the quality of the
link cannot be determined by measuring the far-end eye opening at the receiver pins. At high line
rates, the received eye measured on the printed circuit board can appear to be completely closed
even though the internal eye after the receiver equalizer is open.
The 7 series FPGAs GTP transceivers RX eye scan provides a mechanism to measure and visualize
the receiver eye margin after the equalizer. Additional use modes enable several other methods to
determine and diagnose the effects of equalization settings.
X-Ref Target - Figure 4-20
Figure 4-20: Offset Sample and Data Sample to Calculate BER as a Function of Offset—the Statistical Eye
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The sequence of events in Figure 4-19
To change RXRATE, a DRP write must be issued to the GTPE2_CHANNEL primitive,
DRPADDR 9'h011, set bit[11] to 1'b0.
a. To ensure only bit[11] of DRPADDR 9'h011 is modified, a read-modify-write function
must be performed.
Upon DRP write completion, the value of RXRATE must be changed to the new desired setting.
Wait for RXPMARESETDONE to be detected low.
Issue DRP write to the GTPE2_CHANNEL primitive, DRPADDR 9'h011, restoring the
original setting for bit[11]. The completion of this DRP write must occur before
RXPMARESETDONE switches from low to high. RXPMARESETDONE will stay low for a
minimum of 0.66 µs.
This sequence will simulate correctly if SIM_RESET_SPEEDUP is set to FALSE. If
SIM_RESET_SPEEDUP is set to TRUE, this sequence should be bypassed.
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7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
UG482_c4_09_110911