Xilinx 7 Series User Manual page 108

Chapter 3: Transmitter
X-Ref Target - Figure 3-20
TXP/N
PLL0OUTCLK
PLL1OUTCLK
PLL0 PLL1
REFCLK Sel REFCLK Sel
GTPE2_
COMMON
REFCLK Distribution
IBUFDS_GTE2
MGTREFCLK[0/1]P
MGTREFCLK[0/1]N
Notes relevant to
1.
2.
3.
4.
5.
108
Send Feedback
TX PMA
TXDATA
PISO
/D
Phase
/4 or
{1,2,
Interp
/5
4,8}
TXSYSCLKSEL[0]
0 1
PLL0REFCLK
0
PLL1REFCLK
1
TXSYSCLKSEL[1]
GTPE2_CHANNEL (GTP Transceiver Primitive)
O
0
ODIV2
/2 1
REFCLK_CTRL 2
Figure 3-20: TX Serial and Parallel Clock Divider
Figure 3-20:
TXOUTCLKPCS and TXOUTCLKFABRIC are redundant outputs. Use TXOUTCLK for new
designs.
The REFCLK_CTRL option is controlled automatically by software and is not user selectable.
The user can only route one of the IBUFDS_GTE2's O or ODIV2 outputs to the FPGA logic.
IBUFDS_GTE2 is a redundant output for additional clocking scheme flexibility.
The selection of the /4 or /5 divider block is controlled by the TX_DATA_WIDTH attribute
from the GTPE2_CHANNEL primitive. /4 is selected when TX_DATA_WIDTH = 16 or 32. /
5 is selected when TX_DATA_WIDTH = 20 or 40.
For details about placement constraints and restrictions on clocking resources (MMCME2,
PLLE2, BUFGCTRL, IBUFDS_GTE2, BUFG, etc.), refer to the UG472, 7 Series FPGAs
Clocking Resources User Guide.
www.xilinx.com
TX Polarity
Control
/2
TX PCS
'1'
000
TXOUTCLKPCS
001
TXOUTCLKPMA
010
TXPLLREFCLK_DIV1
011
TXPLLREFCLK_DIV2
/2 100
TXOUTCLKSEL
7 Series FPGAs GTP Transceivers User Guide
TXDATA From
Upstream
PCS Blocks
TXOUTCLKPCS 1
Delay
0
Aligner
TXOUTCLK
1
TXDLYBYPASS
TXOUTCLKFABRIC 1
IBUFDS_GTE2 Output to Logic 3
UG482_C3_19_021113
UG482 (v1.9) December 19, 2016