Xilinx 7 Series User Manual page 286

Appendix D: DRP Address Map of the GTP Transceiver
Table D-2: DRP Map of GTPE2_CHANNEL Primitive (Cont'd)
DRP
DRP Bits
Address
0016
5:0
(Cont'd)
15:11
0017
10:6
0017
7:0
0018
15
0019
12
0019
11:9
0019
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R/W Attribute Name
R/W SATA_MAX_INIT
R/W RXOSCALRESET_TIMEOUT
R/W RXOSCALRESET_TIME
R/W TRANS_TIME_RATE
R/W PMA_LOOPBACK_CFG
R/W TX_PREDRIVER_MODE
R/W TX_EIDLE_DEASSERT_DELAY
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Attribute Attribute
Bits Encoding
38
39
40
41
42
43
44
45
46
47
48
49
50
5:0
51
52
53
54
55
56
57
58
59
60
61
62
63
4:0 0-31
4:0 0-31
7:0 0-255
0 0-1
0 0-1
2:0 0-7
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
DRP
Encoding
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
0-31
0-31
0-255
0-1
0-1
0-7