Xilinx 7 Series User Manual page 180

Chapter 4: Receiver
Using RX Buffer Bypass in Multi-Lane Manual Mode
For GTP transceivers, phase alignment can be performed manually or automatically.
This section describes the steps required to perform the multi-lane RX buffer bypass alignment
procedure manually:
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Figure 4-38
X-Ref Target - Figure 4-38
These GTP transceiver settings should be used to bypass the RX elastic buffer:
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With the RX recovered clock selected, RXOUTCLK is to be used as the source of RXUSRCLK.
The user must ensure that RXOUTCLK and the selected RX recovered clock are operating at the
desired frequency. When the RX elastic buffer is bypassed, the RX phase alignment procedure must
be performed after these conditions:
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180
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Master: In a multi-lane application, the buffer bypass master is the lane that is the source of
RXOUTCLK.
Slave: All the lanes that share the same RXUSRCLK/RXUSRCLK2, which is generated from
the RXOUTCLK of the buffer bypass master.
shows an example of buffer bypass master versus slave lanes.
Slave
GTP RX
Lane 3
RXUSRCLK
RXUSRCLK2
Master
GTP RX
Lane 2
RXUSRCLK
RXUSRCLK2
Slave
GTP RX
Lane 1
RXUSRCLK
RXUSRCLK2
Slave
GTP RX
Lane 0
RXUSRCLK
RXUSRCLK2
Figure 4-38: Example of RX Buffer Bypass Master versus Slave Lanes
RXBUF_EN = FALSE
RX_XCLK_SEL = RXUSR
RXOUTCLKSEL = 010 to select the RX recovered clock as the source of RXOUTCLK
RXDDIEN = 1
Resetting or powering up the GTP transceiver receiver
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MMCM/PLL
RXOUTCLK
BUFG
7 Series FPGAs GTP Transceivers User Guide
BUFG
UG482_c4_138_020613
UG482 (v1.9) December 19, 2016