Xilinx 7 Series User Manual page 91

Figure 3-9
external sequence counter mode with 64B/66B encoding.
X-Ref Target - Figure 3-9
TXUSRCLK2
TXHEADER[1:0]
TXSEQUENCE[5:0]
28
TXDATA[31:0]
D a
Figure 3-10
external sequence counter mode with 64B/67B encoding.
X-Ref Target - Figure 3-10
The sequence of transmitting 64/67 data for the external sequence counter mode is:
1.
2.
3.
4.
5.
6.
7.
8.
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
shows how a pause occurs at counter value 31 when using an 4-byte fabric interface in
1
29 30 31 32
D b D c D d
Figure 3-9: Pause at Sequence Counter Value 31
shows how a pause occurs at counter value 44 when using a 2-byte fabric interface in
TXUSRCLK2
TXHEADER[2:0]
2
TXSEQUENCE[6:0]
42
TXDATA[15:0]
D a
Figure 3-10: Pause at Sequence Counter Value 44
Apply GTTXRESET and wait until the reset cycle is completed.
During reset, apply 7'h00 to TXSEQUENCE, header information to TXHEADER, and initial
data to TXDATA. This state can be held indefinitely until data transmission is ready.
On count 0, apply data to TXDATA and header information to TXHEADER. For a 2-byte
interface (TX_DATA_WIDTH = 16), drive the second 2 bytes to TXDATA while still on count
0.
The sequence counter increments to 1 while data is driven on TXDATA.
After applying 4 bytes of data, the counter increments to 2. Apply data on TXDATA and header
information on TXHEADER.
On count 21, stop data pipeline.
On count 22, drive data on TXDATA.
On count 44, stop data pipeline.
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2
0 1 2 3
D e D f D g D h
Pause for 1 TXUSRCLK2 cycle.
Data is ignored.
43 44
D b D c
TX Gearbox
1
4 5 6
D i D j D k
UG482_c3_09_110911
1
45 46
D d D e D f D g
Pause for 2 TXUSRCLK2 cycle.
Data is ignored.
UG482_c3_10_110911
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