Xilinx 7 Series User Manual page 243

X-Ref Target - Figure A-6
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
XC7A75T:
GTPE2_CHANNEL_X0Y3
XC7A100T:
GTPE2_CHANNEL_X0Y3
XC7A75T:
GTPE2_CHANNEL_X0Y2
XC7A100T:
GTPE2_CHANNEL_X0Y2
XC7A75T:
GTPE2_COMMON_X0Y0
XC7A100T:
GTPE2_COMMON_X0Y0
XC7A75T:
GTPE2_CHANNEL_X0Y1
XC7A100T:
GTPE2_CHANNEL_X0Y1
XC7A75T:
GTPE2_CHANNEL_X0Y0
XC7A100T:
GTPE2_CHANNEL_X0Y0
Figure A-6: Placement Diagram for the FGG676 Package (2 of 2)
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FGG676 Package Placement Diagram
AE7 MGTPTXP3_213
AF7 MGTPTXN3_213
AE11 MGTPRXP3_213
AF11 MGTPRXN3_213
AC8 MGTPTXP2_213
AD8 MGTPTXN2_213
AC14 MGTPRXP2_213
AD14 MGTPRXN2_213
AA11 MGTREFCLK1P_213
AB11 MGTREFCLK1N_213
AA13 MGTREFCLK0P_213
AB13 MGTREFCLK0N_213
AE9 MGTPTXP1_213
AF9 MGTPTXN1_213
AE13 MGTPRXP1_213
AF13 MGTPRXN1_213
AC10 MGTPTXP0_213
AD10 MGTPTXN0_213
AC12 MGTPRXP0_213
AD12 MGTPRXN0_213
UG482_aA_03_080513
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