Tx Polarity Control - Xilinx 7 Series User Manual

Chapter 3: Transmitter
X-Ref Target - Figure 3-18
TXPRBSSEL
TXPRBSFORCEERR
RXPRBS_ERR_LOOPBACK =0
RXPRBSSEL
RXPRBSERR
RX_PRBS_ERR_CNT
To calculate accurately the receiver's bit error rate (BER), an external jitter tolerance tester should
be used. For the test, the GTP transceiver should loop the received error status back through the
transmitter by setting RXPRBS_ERR_LOOPBACK to 1
applied to RXPRBSSEL and TXPRBSSEL.
X-Ref Target - Figure 3-19
Jitter Tester
Figure 3-19: Jitter Tolerance Test Mode with a PRBS-7 Pattern

TX Polarity Control

Functional Description
If TXP and TXN differential traces are accidentally swapped on the PCB, the differential data
transmitted by the GTP transceiver TX is reversed. One solution is to invert the parallel data before
serialization and transmission to offset the reversed polarity on the differential pair. The TX polarity
control can be accessed through the TXPOLARITY input from the fabric user interface. It is driven
High to invert the polarity of outgoing data.
106
Send Feedback
001
TX Pattern
Generator
001
RX Pattern
Checker
Figure 3-18: Link Test Mode with a PRBS-7 Pattern
TX
PRBS-7 pattern
with jitter
RX
Pattern
Checker
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001
RXPRBSSEL
RX Pattern
Checker
RXPRBSERR
RX_PRBS_ERR_CNT
RXPRBS_ERR_LOOPBACK =0
001
TXPRBSSEL
TX Pattern
Generator
TXPRBSFORCEERR
(Figure 3-19). The same setting should be
001
RXPRBSSEL
RX Pattern
Checker
RXPRBSERR
RX_PRBS_ERR_CNT
RXPRBS_ERR_LOOPBACK =1
001
TXPRBSSEL
TX Pattern
Generator
TXPRBSFORCEERR
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
UG482_c3_17_110911
UG482_c3_18_110911