Xilinx 7 Series User Manual page 89

TX Gearbox Operating Modes
The GTP transceiver's TX gearbox only supports the external sequence counter mode and this must
be implemented in user logic. The TX gearbox supports 2-byte and 4-byte interfaces to the FPGA
logic.
External Sequence Counter Operating Mode
As shown in
[6:0], TXDATA[31:0], and TXHEADER[2:0] inputs. A binary counter must exist in the user logic
to drive the TXSEQUENCE port. For 64B/66B encoding, the counter increments from 0 to 32 and
repeats from 0. For 64B/67B encoding, the counter increments from 0 to 66 and repeats from 0.
When using 64B/66B encoding, tie TXSQUENCE [6] to logic 0 and tie the unused TXHEADER [2]
to logic 0. The sequence counter increment ranges ({0 to 32}, {0 to 66}) are identical for 2-byte and
4-byte interfaces. However, the counter must increment once every two TXUSRCLK2 cycles when
using a 2-byte interface and every TXUSRCLK2 cycle when using a 4-byte interface.
X-Ref Target - Figure 3-8
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
Figure 3-8, the external sequence counter operating mode uses the TXSEQUENCE
TX Gearbox
(in 7 Series FPGAs
GTP Transceiver)
Figure 3-8: TX Gearbox in External Sequence Counter Mode
www.xilinx.com
TXDATA[15:0] or TXDATA[31:0]
TXHEADER[2:0]
TXSEQUENCE[6:0]
TX Gearbox
Design in FPGA Logic
Data Source
Pause
Sequence Counter
(0–32 or 0–66)
UG482_c3_08_110911
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