Tx Receiver Detect Support For Pci Express Designs - Xilinx 7 Series User Manual

TX Receiver Detect Support for PCI Express Designs

Functional Description
The PCI Express specification includes a feature that allows the transmitter on a given link to detect
if a receiver is present. The decision if a receiver is present is based on the rise time of TXP/TXN.
Figure 3-22
P1 power down state to perform receiver detection. Receiver detection requires a 75 nF to 200 nF
external coupling capacitor between the transmitter and receiver, and the receiver must be
terminated to GND. The receiver detection sequence starts with the assertion of TXDETECTRX. In
response, the receiver detection logic drives TXN and TXP to (V
them. After a programmable interval, the levels of TXN and TXP are compared with a threshold
voltage. At the end of the sequence, the receiver detection status is presented on RXSTATUS when
PHYSTATUS is asserted High for one cycle.
X-Ref Target - Figure 3-22
Ports and Attributes
Table 3-30
Table 3-30: TX Receiver Detection Ports
TXDETECTRX
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
shows the circuit model used for receive detection. The GTP transceiver must be in the
V
DD
R : 40Ω – 60Ω
TERMT
TXP
TXDETECTRX
GTP Transceiver
Components
Figure 3-22: Receiver Detection Circuit Model
describes the TX receiver detection ports.
Port Dir Clock Domain
In TXUSRCLK2
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TX Receiver Detect Support for PCI Express Designs
DD
C : 75 nF - 200 nF
AC
C : < 3 nF
CH
Channel
Components
Used to tell the GTP transceiver to begin a
receiver detection operation.
0: Normal operation.
1: Receiver detection.
- V /2) and then releases
SWING
R : 40Ω – 60Ω
TERMR
V
TERMR
Far-End Receiver
Components
UG482_c3_21_110911
Description
121
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