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Xilinx RocketIO X User Manual

Xilinx RocketIO X User Manual

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RocketIO™ X
Transceiver

User Guide

UG035 (v1.5) November 22, 2004
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  • Page 1: User Guide

    RocketIO™ X Transceiver User Guide UG035 (v1.5) November 22, 2004...
  • Page 2 Xilinx, Inc. assumes no obligation to correct any errors contained herein or to advise any user of this text of any correction if such be made. Xilinx, Inc. will not assume any liability for the accuracy or correctness of any engineering or software support or assistance provided to a user.
  • Page 3 RXLOSSOFSYNC[1:0], RXNOTINTABLE[7:0], RXRUNDISP[7:0], RXUSRCLK, RXUSRCLK2, TXBYPASS8B10B[7:0], TXCHARDISPMODE[7:0], TXCHARDISPVAL[7:0], TXCHARISK[7:0], TXDATA[63:0], TXDATAWIDTH[1:0], TXGEARBOX64B66BUSE, TXINTDATAWIDTH[1:0], TXKERR[7:0], TXRUNDISP[7:0], TXSCRAM64B66BUSE, TXUSRCLK, and TXUSRCLK2. • Updated RocketIO X Transceiver Attributes, Table 1-5, page 35. Made changes to: ALIGN_COMMA_WORD, CHAN_BOND_MODE, CHAN_BOND_SEQ_1_*[10:0], CLK_COR_8B10B_DE, CLK_COR_MAX_LAT, CLK_COR_MIN_LAT, CLK_COR_SEQ_2_USE, CLK_COR_SEQ_LEN, and RX_LOSS_OF_SYNC_FSM.
  • Page 4 Appendix D, “Virtex-II Pro to Virtex-II Pro X FPGA Design Migration: • Added note directly above Figure D-2, page 171. • Added new section, “Migration Differences.” Added new “Index.” RocketIO™ X Transceiver User Guide www.xilinx.com UG035 (v1.5) November 22, 2004 1-800-255-7778...
  • Page 5 • Added PMA attributes and updated Table C-2, page 148; added new PMA attribute definitions. • Added XAPP762 and XAPP767 to Appendix G, “Related Online Documents.”Also added RPT007 to “Characterization Reports.” UG035 (v1.5) November 22, 2004 www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778...
  • Page 6 RocketIO™ X Transceiver User Guide www.xilinx.com UG035 (v1.5) November 22, 2004 1-800-255-7778...

  • Page 7: Table Of Contents

    Typographical ............23 Chapter 1: RocketIO X Transceiver Overview Basic Architecture and Capabilities .
  • Page 8 Receiver Lock Control ........... . 104 UG035 (v1.5) November 22, 2004 www.xilinx.com RocketIO™ X Transceiver User Guide...
  • Page 9 Powering the RocketIO X Transceivers ........
  • Page 10 ......... 172 UG035 (v1.5) November 22, 2004 www.xilinx.com RocketIO™ X Transceiver User Guide...
  • Page 11 XAPP752: Virtex-II Pro X OC-48 Jitter Compliance Test Results ....199 XAPP762: RocketIO X Bit-Error Rate Tester Reference Design....199 XAPP767: RocketIO X Transceiver Clock Mode Switcher for Virtex-II Pro X FPGAs .
  • Page 12 RocketIO™ X Transceiver User Guide www.xilinx.com UG035 (v1.5) November 22, 2004 1-800-255-7778...
  • Page 13 Chapter 1: RocketIO X Transceiver Overview Figure 1-1: RocketIO X Transceiver Block Diagram ....... 26 Chapter 2: Digital Design Considerations Figure 2-1: Transmit Architecture .
  • Page 14 Appendix A: RocketIO X Transceiver Timing Model Figure A-1: RocketIO X Transceiver Block Diagram......131 Figure A-2: RocketIO X Transceiver Timing Relative to Clock Edge .
  • Page 15 Figure E-2: Backdrilled vs Non-Backdrilled Channel Characteristics....178 Appendix F: Modifiable Attributes Appendix G: Related Online Documents UG035 (v1.5) November 22, 2004 www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778...
  • Page 16 RocketIO™ X Transceiver User Guide www.xilinx.com UG035 (v1.5) November 22, 2004 1-800-255-7778...
  • Page 17 Table 1-5: RocketIO X Transceiver Attributes ........
  • Page 18 Table A-1: RocketIO X Clock Descriptions ........
  • Page 19 GT10_XAUI_4 ............193 Table F-8: Default Attribute Values: GT10_OC192_4 and GT10_OC192_8... 195 UG035 (v1.5) November 22, 2004 www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778...
  • Page 20 GT10_OC48_4 ............. 197 Appendix G: Related Online Documents RocketIO™ X Transceiver User Guide www.xilinx.com UG035 (v1.5) November 22, 2004 1-800-255-7778...

  • Page 21: Preface: About This Guide

    Preface About This Guide RocketIO X Features RocketIO X transceivers have flexible, programmable features that allow a multi-gigabit serial transceiver (MGT) to be easily integrated into any Virtex-II Pro X design: • Variable speed full-duplex transceiver, allowing 2.488 Gb/s to 10.3125 Gb/s baud...

  • Page 22: Related Information

    Appendix E, “Serial Backplane System Design” – Additional PCB design guidelines to meet the demands of the RocketIO X transceiver for operation above 3.125 Gb/s. Related Information For a complete menu of online information resources available on the Xilinx website, visit http://www.xilinx.com/virtex2pro...

  • Page 23: User Guide Conventions

    This document uses the following conventions. An example illustrates each convention. Port and Attribute Names Input and output ports of the RocketIO X transceiver primitives are denoted in upper-case letters. Attributes of the RocketIO X transceiver are denoted in upper-case letters with underscores.
  • Page 24 Preface: About This Guide www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778 UG035 (v1.5) November 22, 2004...

  • Page 25: Chapter 1: Rocketio X Transceiver Overview

    XC2VPX70 Definitions: • Attribute – An attribute is a control parameter to configure the RocketIO X transceiver. There are both primitive ports (traditional I/O ports for control and status) and transceiver attributes. Transceiver attributes are also controls to the transceiver that regulate data widths and encoding rules, but controls that are configured as a group in “soft”...

  • Page 26: Figure 1-1: Rocketio X Transceiver Block Diagram

    PMAREGSTROBE PMARXLOCKSEL[1:0] PMARXLOCK REFCLKBSEL RXBLCOKSYNC64B66BUSE RXCOMMADETUSE RXDATAWIDTH[1:0] RXDECC64B66BUSE RXDEC8B10BUSE RXDESCRAM64B66BUSE RXIGNOREBTF RXINTDATAWIDTH[1:0] RXSLIDE TXDATAWIDTH[1:0] TXENC64B66BUSE TXENC8B10BUSE TXGEARBOX64B66BUSE TXINTDATAWIDTH[1:0] TXSCRAM64B66BUSE TXOUTCLK UG035_01_111303 Figure 1-1: RocketIO X Transceiver Block Diagram www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778 UG035 (v1.5) November 22, 2004...

  • Page 27: Table 1-2: Communications Standards Supported By Rocketio X Transceiver

    10GE XAUI, 2-byte data path GT10_AURORAX_8 Xilinx 10G protocol, 8-byte data path There are three ways to configure the RocketIO X transceiver: • Static properties can be set through attributes in the HDL code. Use of attributes are covered in detail in “Primitive Attributes,”...

  • Page 28: Rocketio X Transceiver Instantiations

    Chapter 1: RocketIO X Transceiver Overview The RocketIO X transceiver consists of the Physical Media Attachment (PMA) and Physical Coding Sublayer (PCS). The PMA contains the serializer/deserializer (SERDES), TX and RX buffers, clock generator, and clock recovery circuitry. The PCS contains the 8B/10B encoder/decoder, 64B/66B encoder/decoder/scrambler/descrambler, and the elastic buffer supporting channel bonding and clock correction.
  • Page 29 RXCHARISCOMMA[7:0] 1, 2, 4, 8 Indicates the reception of K28.0, K28.5, K28.7, and some out of band commas (depending on the setting of DEC_VALID_COMMA_ONLY by the 8B/10B decoder. RocketIO™ X Transceiver User Guide www.xilinx.com UG035 (v1.5) November 22, 2004 1-800-255-7778...
  • Page 30 Chapter 1: RocketIO X Transceiver Overview Table 1-4: Primitive Ports (Continued) Port Port Size Definition RXCHARISK[7:0] 1, 2, 4, 8 If 8B/10B decoding is enabled, it indicates that the received data is a “K” character when asserted. Included in Byte- mapping.
  • Page 31 TXBUFERR Provides status of the transmission FIFO. If asserted High, an overflow/underflow has occurred. When this bit becomes set, it can only be reset by asserting TXRESET. RocketIO™ X Transceiver User Guide www.xilinx.com UG035 (v1.5) November 22, 2004 1-800-255-7778...
  • Page 32 Chapter 1: RocketIO X Transceiver Overview Table 1-4: Primitive Ports (Continued) Port Port Size Definition TXBYPASS8B10B[7:0] If TXENC8B10BUSE = 1 and TXENC64B66BUSE = 0 (8B/10B encoder enabled and 64B/66B encoder disabled), each bit of TXBYPASS8B10B[7:0] controls the bypass of the corresponding TXDATA byte;...
  • Page 33 Indicates even boundary for bypassing in 64B/66B mode. Transmit differential port (FPGA external) TXOUTCLK Synthesized Clock from RocketIO X transmitter. This clock can be scaled (e.g., for 64B/66B) relative to BREFCLK, depending upon the specific operating mode of the transmitter.
  • Page 34 Chapter 1: RocketIO X Transceiver Overview Table 1-4: Primitive Ports (Continued) Port Port Size Definition TXUSRCLK Clock output from a DCM that is clocked with the REFCLK (or other reference clock). This clock is used for writing the TX buffer and is frequency-locked to the REFCLK.

  • Page 35: Primitive Attributes

    See Appendix F, “Modifiable Attributes” (Table F-1through Table F-9) for the default values of each primitive. Table 1-5: RocketIO X Transceiver Attributes Attribute Type Description ALIGN_COMMA_WORD Integer Integer (1, 2, 4) controls the alignment of detected commas within the transceiver’s 4-byte wide data path.
  • Page 36 Chapter 1: RocketIO X Transceiver Overview Table 1-5: RocketIO X Transceiver Attributes (Continued) Attribute Type Description CHAN_BOND_SEQ_1_*[10:0] 11-bit These define the channel bonding sequence. The usage of these vector vectors also depends on CHAN_BOND_SEQ_LEN and CHAN_BOND_SEQ_2_USE. See “Transmitting Vitesse Channel Bonding Sequence,”...
  • Page 37 Primitive Attributes Table 1-5: RocketIO X Transceiver Attributes (Continued) Attribute Type Description CLK_COR_SEQ_2_MASK[3:0] 4-bit Each bit of the mask determines if that particular sequence is vector detected regardless of its value. If bit 0 is High, then CLK_COR_SEQ_2_1 is matched regardless of its value.
  • Page 38 Chapter 1: RocketIO X Transceiver Overview Table 1-5: RocketIO X Transceiver Attributes (Continued) Attribute Type Description MCOMMA_10B_VALUE[9:0] 10-bit These define minus-comma for the purpose of raising vector RXCOMMADET and realigning the serial bit stream byte boundary. This definition does not affect 8B/10B encoding or decoding. Also see COMMA_10B_MASK.

  • Page 39: Modifiable Attributes

    (TXCHARISK[0]) correlating to the data bits TXDATA[7:0]. Table 1-6: Control/Status Bus Association to Data Bus Byte Paths Control/Status Bit Data Bits [7:0] [15:8] [23:16] [31:24] [39:32] [47:40] [55:48] [64:56] RocketIO™ X Transceiver User Guide www.xilinx.com UG035 (v1.5) November 22, 2004 1-800-255-7778...
  • Page 40 Chapter 1: RocketIO X Transceiver Overview www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778 UG035 (v1.5) November 22, 2004...

  • Page 41: Chapter 2: Digital Design Considerations

    64B/66B (32 bit internal). Note: The information in this chapter is provided to RocketIO X users as a reference for understanding the individual attribute and control port settings within a primitive. Users have the choice of using the supported primitives in...

  • Page 42: Top-Level Architecture

    RX Elastic Comma Detect Block Buffer Align Descr Sync 16x52 Decode HOLDOFF RXDATA Fabric RXUSRCLK RXRECCLK RXUSRCLK2 RXDEC8B10BUSE, RX_BUFFER_USE RXDESCRAM64B66BUSE RXBLOCKSYNCUSE, RXDEC6466USE RXVALUEDETUSE UG035_CH3_02_092903 Figure 2-2: Receive Architecture www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778 UG035 (v1.5) November 22, 2004...

  • Page 43: Operation Modes

    PCS. Typically, these signals would be the first consideration after the mode of operation has been selected: • RXDATAWIDTH[1:0] • RXINTDATAWIDTH[1:0] • TXDATAWIDTH[1:0] • TXINTDATAWIDTH[1:0] RocketIO™ X Transceiver User Guide www.xilinx.com UG035 (v1.5) November 22, 2004 1-800-255-7778...

  • Page 44: Dynamic Signals

    • MCOMMA_10B_VALUE • PCOMMA_10B_VALUE • COMMA_10B_MASK • RXCHARISCOMMA[7:0] • RXCHARISK[7:0] www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778 UG035 (v1.5) November 22, 2004...
  • Page 45 The following dynamic signals control internal states of the PCS: • RXSLIDE • CHBONDI[4:0] The following dynamic signals affect the control registers of the PMA: • PMAREGADDR[5:0] • PMAREGDATAIN[7:0] • PMAREGRW • PMAREGSTROBE RocketIO™ X Transceiver User Guide www.xilinx.com UG035 (v1.5) November 22, 2004 1-800-255-7778...

  • Page 46: Bus Interface

    2-Byte Internal Data Width 4-Byte Internal Data Width 1 byte 2 byte 4 byte 8 byte Notes: 1. Each edge of slower clock must align with falling edge of faster clock. www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778 UG035 (v1.5) November 22, 2004...

  • Page 47: 8B/10B

    Block Level Functions 8B/10B Note: In the RocketIO transceiver, the most significant byte was sent first; in the RocketIO X transceiver the least significant byte is sent first. The following sections categorize the ports and attributes of the transceiver according to...

  • Page 48: Encoder

    40-bit and 80-bit wide buses). TXCHARDISPVAL becomes bits 8, 18, 28, 38, 48, 58, 68, and 78 of the transmit data bus while the TXDATA bus completes the bus. See Table 2-6. www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778 UG035 (v1.5) November 22, 2004...

  • Page 49: Figure 2-5: 10-Bit Tx Data Map With 8B/10B Bypassed

    TXRUNDISP is a status port that is byte-mapped to the TXDATA. This port indicates the running disparity after this byte of TXDATA is encoded. When asserted, the disparity is positive. When de-asserted, the disparity is negative. RocketIO™ X Transceiver User Guide www.xilinx.com UG035 (v1.5) November 22, 2004 1-800-255-7778...

  • Page 50: Decoder

    Bits “b” and “a,” respectively, of the 10-bit encoded data that the transceiver passes on to the user logic. Table 2-7 illustrates the RX data map during 8B/10B bypass. www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778 UG035 (v1.5) November 22, 2004...

  • Page 51: Rxcharisk And Rxrundisp

    RXNOTINTABLE is asserted whenever the received data is not in the 8B/10B tables. The data received on bytes marked by RXNOTINTABLE are invalid. This port is also byte- mapped to RXDATA and is only used when the 8B/10B decoder is enabled. RocketIO™ X Transceiver User Guide www.xilinx.com UG035 (v1.5) November 22, 2004 1-800-255-7778...

  • Page 52: Vitesse Disparity Example

    K28.5- (or K28.5+) 0 1 0 1 10111100 K28.5- (or K28.5+) The RocketIO X core receives this data but must have the CHAN_BOND_SEQ set with the disp_err bit set High for the cases when TXCHARDISPVAL is set High during data transmission.

  • Page 53: Comma Detection

    The DEC_MCOMMA_DETECT and DEC_PCOMMA_DETECT indicate which symbol should be compared to the incoming data for alignment. See Table 2-8. RocketIO™ X Transceiver User Guide www.xilinx.com UG035 (v1.5) November 22, 2004 1-800-255-7778...

  • Page 54: Setting Mcomma_10B_Value, Pcomma_10B_Value, And Comma_10B_Mask (Special Note)

    To detect values listed in the 8b/10b tables, simply reverse the values in the tables. To detect SONET type values, the exact value can be used without reversal. www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778 UG035 (v1.5) November 22, 2004...

  • Page 55: Alignment

    No alignment takes place. If a positive symbol is detected, alignment takes place at that symbol location. If a negative symbol is detected, alignment takes place at that symbol location. RocketIO™ X Transceiver User Guide www.xilinx.com UG035 (v1.5) November 22, 2004 1-800-255-7778...
  • Page 56 –1. When RXSLIDE is asserted High, it must be asserted Low for two clock periods before it can be asserted High again. This functionality can be used for applications such as SONET. www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778...

  • Page 57: 64B/66B

    Table 2-11: Transmit 64B/66B Encoder Control Mapping TXC[3:0] (TXCHARISK[3:0]) Block Formatting 1111 Idles OR terminate-with-idles 0001 Start-of-frame OR ordered-set 1110 Terminate in second position 1100 Terminate in third position RocketIO™ X Transceiver User Guide www.xilinx.com UG035 (v1.5) November 22, 2004 1-800-255-7778...

  • Page 58: Chapter 2: Digital Design Considerations

    Data Block Format Block Type Control Block Formats Field 0x1e 0x2d 0x33 0x66 0x55 0x78 0x4b 0x87 0x99 0xaa 0xb4 0xcc 0xd2 0xe1 0xff UG035_ch3_23_091103 Figure 2-8: Block Format Function www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778 UG035 (v1.5) November 22, 2004...

  • Page 59: Scrambler

    0 scrambler not used TXSCRAM64B66BUSE 1 scrambler enabled Note: When using the 64B/66B scrambler, the Gearbox must also be enabled (Always set to TXSCRAM64BB66USE = TXGEARBOX64B66BUSE) RocketIO™ X Transceiver User Guide www.xilinx.com UG035 (v1.5) November 22, 2004 1-800-255-7778...

  • Page 60: Gearbox

    If the signal RXDESCRAM64B66BUSE is deasserted Low, the descrambler is not used. Normal Operation If the signal RXDESCRAM64B66BUSE is asserted High, the descrambler is enabled for use. The descrambler uses the polynomial: G(x) = 1 + x www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778 UG035 (v1.5) November 22, 2004...

  • Page 61: Block Sync

    This process of slipping and testing the sync header repeats until block lock is achieved. RocketIO™ X Transceiver User Guide www.xilinx.com UG035 (v1.5) November 22, 2004 1-800-255-7778...

  • Page 62: Figure 2-9: Block Sync State Machine

    = 64* block_lock sh_invalid_cnt = 16 + sh_invalid_cnt = 0 !block_lock 64_GOOD SLIP block_lock <=true block_lock <=false SLIP <=true slip_done ug035_ch3_21_090903 Figure 2-9: Block Sync State Machine www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778 UG035 (v1.5) November 22, 2004...

  • Page 63: Functions Common To All Protocols

    FIFO is less than this value, idles are inserted so that the latency through the receive FIFO are greater than CLK_COR_MIN_LAT. A correction to the latency due to a CLK_COR_MAX_LAT violation is never less than RocketIO™ X Transceiver User Guide www.xilinx.com UG035 (v1.5) November 22, 2004 1-800-255-7778...

  • Page 64: Clock Correction Sequences

    0, disparity error required, char is K, 8-bit data value (after 8B/10B decoding, depends on CLK_COR_8B10B_DE) • 0, 10-bit data value (without 8B/10B decoding, depends on CLK_COR_8B10B_DE) • 1, xx, sync character (with 64B/66B encoding • 1, xx, 8-bit data value www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778 UG035 (v1.5) November 22, 2004...

  • Page 65: Determining Correct Clk_Cor_Min_Lat

    Example: The channel bond character is 0x000000FF. If this sequence of data is sent: 000000FF 01020304 05060708 09000000 FF010203 04050607 The result is: 000000FF 01020304 05060708 000000FF 01020304 RocketIO™ X Transceiver User Guide www.xilinx.com UG035 (v1.5) November 22, 2004 1-800-255-7778...

  • Page 66: Figure 2-10: Daisy-Chained Transceiver Chbondi/Chbondo Buses

    Whether a slave is a 1-hop or 2-hop slave, internal logic causes the data driven on the CHBONDO bus from the master to be recognized by the slaves at the same time and must www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778 UG035 (v1.5) November 22, 2004...

  • Page 67: Figure 2-11: Xc2Vpx20 Device Implementation

    CHBONDO CHBONDI CHBONDO CHBONDI CHBONDO CHBONDI CHBONDO CHBONDI CHBONDO CHBONDI CHBONDO CHBONDI SLAVE_2_HOPS SLAVE_2_HOPS SLAVE_2_HOPS SLAVE_2_HOPS SLAVE_1_HOP SLAVE_2_HOPS SLAVE_2_HOPS SLAVE_2_HOPS SLAVE_2_HOPS SLAVE_2_HOPS UG035_ch2_11_051904 Figure 2-12: XC2VPX70 Device Implementation RocketIO™ X Transceiver User Guide www.xilinx.com UG035 (v1.5) November 22, 2004 1-800-255-7778...

  • Page 68: Status And Event Bus

    Table 2-16: Signal Values for a Channel Bonding Skew Status CHBONDDONE RXBUFSTATUS RXCLKCORCNT STATUS INDICATOR 1'b0 2’b01 3’b001 DATA0 1'b0 2’b00 cbSkew[5:3] DATA1 1'b0 2’b00 cbSkew[2:0] www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778 UG035 (v1.5) November 22, 2004...

  • Page 69: Event Indication

    [1:0] RXBUFSTATUS; input [2:0] RXCLKCORCNT; output cc_event_insert; output cc_event_remove; output cb_event_load; output err_event_cc; output err_event_cb; output [5:0] pointerDiff; output rxbuf_almost_err; output [5:0] cbSkew; ////////////////////////////////////////////////////////////////////// //Signal declaration ////////////////////////////////////////////////////////////////////// RocketIO™ X Transceiver User Guide www.xilinx.com UG035 (v1.5) November 22, 2004 1-800-255-7778...
  • Page 70 <= status_event_bus == ERR_EVENT_CC_C; err_event_cb <= status_event_bus == ERR_EVENT_CB_C; ////////////////////////////////////////////////////////////////////// // Logic to decode the cbSkew value and pointerDiff value ////////////////////////////////////////////////////////////////////// always @(posedge RXUSRCLK2 or posedge DCM_LOCKED_N) begin www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778 UG035 (v1.5) November 22, 2004...
  • Page 71 // Generate RX Elastic Buffer almost error ////////////////////////////////////////////////////////////////////// always @(posedge RXUSRCLK2 or posedge DCM_LOCKED_N) begin if (DCM_LOCKED_N) rxbuf_almost_err <= 1'b0; else rxbuf_almost_err <= (pointerDiff < 6) | (pointerDiff > 57); RocketIO™ X Transceiver User Guide www.xilinx.com UG035 (v1.5) November 22, 2004 1-800-255-7778...
  • Page 72 Chapter 2: Digital Design Considerations endmodule www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778 UG035 (v1.5) November 22, 2004...

  • Page 73: Chapter 3: Clocking And Clock Domains

    Figure 3-1. The reference clocks connect to the REFCLK, REFCLK2, or BREFCLK of the RocketIO X Multi-Gigabit Transceiver (MGT). While only one of these reference clocks is needed to drive the MGT, BREFCLK inputs for the reference clock are recommended for the best operation. All characterization and data sheet numbers use the BREFCLK.

  • Page 74: Clock Ports

    Selects between REFCLK/REFCLK2 and BREFCLK. 0 selects REFCLK/REFCLK2 (based on REFCLKSEL); 1 selects BREFCLK. REFCLKSEL Input Selects which reference clock is used (when REFCLKBSEL=0). 0 selects REFCLK; 1 selects REFCLK2. www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778 UG035 (v1.5) November 22, 2004...

  • Page 75: Use Models

    CLK2X TXUSRCLK CLKDV BUFG USRCLK TXUSRCLK2 CLK0 CLKFB RXUSRCLK USRCLK2 and BUFG User Logic RXUSRCLK2 TXDATA RXDATA User TX & RX Logic RXRECCLK UG035_CH3_03_060304 Figure 3-2: BREFCLK 0:1:1 RocketIO™ X Transceiver User Guide www.xilinx.com UG035 (v1.5) November 22, 2004 1-800-255-7778...

  • Page 76: Figure 3-3: Brefclk 1:1:1

    BUFG CLK2X TXUSRCLK2 CLK0 CLKFB USRCLK RXUSRCLK BUFG RXUSRCLK2 USRCLK2 and User Logic TXDATA RXDATA User TX & RX Logic RXRECCLK DV ratio=2 UG035_CH3_07_060304 Figure 3-4: BREFCLK 2:1:1 www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778 UG035 (v1.5) November 22, 2004...

  • Page 77: Figure 3-5: Txoutclk 1:1:1

    *RXRECCLK should only drive the receive clocks Logic RXDATA DCMs are optional RXRECCLK Using BREFCLK 1:1:1 for TX CLKIN CLK0 BUFG CLKDV CLKFX CLKFB UG035_CH3_13_060304 Figure 3-6: RXRECCLK 1:1:1 RocketIO™ X Transceiver User Guide www.xilinx.com UG035 (v1.5) November 22, 2004 1-800-255-7778...

  • Page 78: 2:1 Use Models

    BREFCLK CLK0 CLKFB RXUSRCLK USRCLK BUFG RXUSRCLK2 USRCLK2 and User Logic TXDATA RXDATA User TX & RX Logic RXRECCLK DV ratio = 2 UG035_CH3_16_060304 Figure 3-8: BREFCLK 2:2:1 www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778 UG035 (v1.5) November 22, 2004...

  • Page 79: Figure 3-9: Txoutclk 2:2:1

    *RXRECCLK should only drive the receive clocks User Logic RXDATA sing option BREFCLK RXRECCLK 2:2:1 for TX DV ratio = 2 CLKIN CLK180 CLKDV CLK0 CLKFB UG035_CH3_18_111604 Figure 3-10: RXRECCLK 2:2:1 RocketIO™ X Transceiver User Guide www.xilinx.com UG035 (v1.5) November 22, 2004 1-800-255-7778...

  • Page 80: 1:2 Use Models

    CLK180 TXUSRCLK BREFCLK CLK2X180 TXUSRCLK2 CLK0 RXUSRCLK CLKFB USRCLK BUFG RXUSRCLK2 USRCLK2 and User Logic TXDATA RXDATA User TX & RX Logic RXRECCLK UG035_CH3_25_060304 Figure 3-12: BREFCLK 1:1:2 www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778 UG035 (v1.5) November 22, 2004...

  • Page 81: Figure 3-13: Brefclk 2:1:2

    Note: Figure 3-15 shows the RocketIO X transceiver instantiated using the recovered clock to clock in the FPGA fabric on the receive side. This can be used to avoid clock correction schemes. The TX can have any of the other 1:2 use models. Also, the waveform only indicates the receive clocks.

  • Page 82: Figure 3-15: Rxrecclk 2:1:2

    CLK0 at *RXRECCLK should only drive the receive clocks RXRECCLK USRCLK2 and User Logic can be implemented to reduce BUFG utilization UG035_CH3_28_060304 Figure 3-15: RXRECCLK 2:1:2 www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778 UG035 (v1.5) November 22, 2004...

  • Page 83: Supported Use Models For Each Pma Mode

    BREFCLK 2:1:1*, TXOUTCLK 1:1:1, RXRECCLK 1:1:1 DCM must be in HF mode 19_80 TXOUTCLK 2:2:1, RXRECCLK 2:2:1 20_40 BREFCLK 2:1:1*, TXOUTCLK 1:1:1, RXRECCLK 1:1:1 DCM must be in HF mode 20_80 TXOUTCLK 2:2:1, RXRECCLK 2:2:1 RocketIO™ X Transceiver User Guide www.xilinx.com UG035 (v1.5) November 22, 2004 1-800-255-7778...
  • Page 84 30_32 BREFCLK 2:2:1, TXOUTCLK 2:2:1, RXRECCLK 2:2:1 31_8 BREFCLK 0:1:2, TXOUTCLK 2:1:2, RXRECCLK 2:1:2 31_16 BREFCLK 0:1:1, TXOUTCLK 1:1:1, RXRECCLK 1:1:1 31_32 BREFCLK 1:2:1, TXOUTCLK 2:2:1, RXRECCLK 2:2:1 www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778 UG035 (v1.5) November 22, 2004...

  • Page 85: Pma

    Clock Domain Architecture The PMA uses the PMA_SPEED attribute to set many aspects of the RocketIO X transceiver for a given serial rate. Many of the aspect set includes analog voltages, biasing, and drive strength optimized for a serial rate range. Other settings define the default equalization and pre-emphasis settings, plus the internal clocks for different internal and external bus widths.
  • Page 86 None/ 8B/10B 23_10 XAUI 3.1875 159.375 318.75 318.75 159.38 318.75 10/8 None/ Fibre 8B/10B Channel 23_20 XAUI 3.1875 159.375 159.375 159.375 159.38 159.375 20/16 None/ Fibre 8B/10B Channel www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778 UG035 (v1.5) November 22, 2004...
  • Page 87 Express/ 8B/10B Infiniban 27_20 20/16 None/8B /10B Express/ Infiniban 27_40 62.5 40/32 None/ Express/ 8B/10B Infiniban 28_10 10/8 None/ 8B/10B Express/ Infiniban 28_20 20/16 None/ 8B/10B Express/ Infiniban RocketIO™ X Transceiver User Guide www.xilinx.com UG035 (v1.5) November 22, 2004 1-800-255-7778...

  • Page 88: Clock Dependency

    For specific timing values, see Module 3 of the Virtex-II Pro data sheet. The timing relationships are further discussed and illustrated in Appendix A, “RocketIO X Transceiver Timing Model.” www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778 UG035 (v1.5) November 22, 2004...

  • Page 89: Data Path Latency

    2 RXCLK0 Interface CommaDET/Align 2-3 RXCLK0 Bypass 1 RXCLK0 Decoding: 8B/10B 2 RXCLK0 + 2 RXUSRCLK 64B/66B 2 RXCLK0 + 3 RXUSRCLK Bypass 1 RXCLK0 + 2 RXUSRCLK RXFIFO RocketIO™ X Transceiver User Guide www.xilinx.com UG035 (v1.5) November 22, 2004 1-800-255-7778...

  • Page 90: Resets And Power Down

    The POWERDOWN signal controls power down within the PCS and PMA. The following table describes the function of the POWERDOWN bus. Table 3-6: Power Control Descriptions POWERDOWN Function PCS and PMA function normally PMA and PCS in powerdown mode www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778 UG035 (v1.5) November 22, 2004...

  • Page 91: Chapter 4: Analog Design Considerations

    CML Output Driver U035_06_091903 Figure 4-1: Differential Amplifier Differential Transmitter The RocketIO X transceiver is implemented in Current Mode Logic (CML). A CML transmitter output consists of transistors configured as shown in Figure 4-1. CML uses a positive supply and offers easy interface requirements. In this configuration, both legs of...

  • Page 92: Output Swing And Emphasis

    Chapter 4: Analog Design Considerations Output Swing and Emphasis The output swing and emphasis levels of the RocketIO X MGTs are fully programmable. Each is controlled via attributes at configuration, but can be modified via partial reconfiguration or the PMA attribute programming bus (Appendix C, “PMA Attribute...

  • Page 93: Figure 4-2: Alternating K28.5+ Without Pre-Emphasis

    Output Swing and Emphasis ug035_ch4_02_091903 Figure 4-2: Alternating K28.5+ Without Pre-Emphasis Logic High Strong High Logic Low Strong Low ug035_ch4__02_091903 Figure 4-3: K28.5+ With Pre-Emphasis RocketIO™ X Transceiver User Guide www.xilinx.com UG035 (v1.5) November 22, 2004 1-800-255-7778...

  • Page 94: Figure 4-5: Eye Diagram: With Pre-Emphasis

    Chapter 4: Analog Design Considerations ug035_ch4_04_091903 Figure 4-4: Eye Diagram: Without Pre-Emphasis ug035_ch4_05_091903 Figure 4-5: Eye Diagram: With Pre-Emphasis www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778 UG035 (v1.5) November 22, 2004...

  • Page 95: Dc Coupled

    11.6dB 9.5dB 8.1dB 7.1dB 120mV 180mV 240mV 300mV 400% 267% 200% 160% 14.0dB 11.3dB 9.5dB 8.3dB 150mV 210mV 360% 257% 13.3dB 11.1dB 120mV 180mV 500% 333% 15.6dB 12.7dB RocketIO™ X Transceiver User Guide www.xilinx.com UG035 (v1.5) November 22, 2004 1-800-255-7778...

  • Page 96: Figure 4-6: Output Swing Versus Pre-Emphasis (%) When Dc Coupled

    Figure 4-6: Output Swing versus Pre-Emphasis (%) When DC Coupled Vos vs. Pre-Emphasis (DC Coupled) 0.00 5.00 10.00 15.00 20.00 Pre-emphasis (dB) Figure 4-7: Output Swing versus Pre-Emphasis (dB) When DC Coupled www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778 UG035 (v1.5) November 22, 2004...

  • Page 97: Table 4-3: Output Swing Versus De-Emphasis (Dc Coupled)

    -6.8dB -6.0dB -5.4dB 570mV 630mV 690mV 750mV 74%1 -11.6dB -9.5dB -8.1dB -7.1dB 600mV 660mV 720mV 780mV -14.0dB -11.3dB -9.5dB -8.3dB 690mV 750mV -13.3dB -11.1dB 720mV 780mV -15.6dB -12.7dB RocketIO™ X Transceiver User Guide www.xilinx.com UG035 (v1.5) November 22, 2004 1-800-255-7778...

  • Page 98: Figure 4-8: Output Swing Versus De-Emphasis (%) When Dc Coupled

    Figure 4-8: Output Swing versus De-Emphasis (%) When DC Coupled Vos vs. De-Emphasis (DC Coupled) 0.00 -5.00 -10.00 -15.00 -20.00 De-emphasis (dB) Figure 4-9: Output Swing versus De-Emphasis (dB) When DC Coupled www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778 UG035 (v1.5) November 22, 2004...

  • Page 99: Ac Coupled

    2.5dB 150mV 210mV 270mV 330mV 120% 6.8dB 5.4dB 4.4dB 3.8dB 120mV 180mV 240mV 200% 133% 100% 9.5dB 7.4dB 6.0dB 150mV 210mV 200% 143% 9.5dB 7.7dB 120mV 300% 12.0dB RocketIO™ X Transceiver User Guide www.xilinx.com UG035 (v1.5) November 22, 2004 1-800-255-7778...

  • Page 100: Figure 4-10: Output Swing Versus Pre-Emphasis (%) When Ac Coupled

    Figure 4-10: Output Swing versus Pre-Emphasis (%) When AC Coupled Vos vs. Pre-Emphasis (AC Coupled) 0.00 5.00 10.00 15.00 20.00 Pre-emphasis (dB) Figure 4-11: Output Swing versus Pre-Emphasis (dB) When AC Coupled www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778 UG035 (v1.5) November 22, 2004...

  • Page 101: Table 4-5: Output Swing Versus De-Emphasis (Ac Coupled)

    360mV 420mV 480mV -6.0dB -4.4dB -3.5dB -2.9dB -2.5dB 330mV 390mV 450mV 510mV -6.8dB -5.4dB -4.4dB -3.8dB 360mV 420mV 480mV -9.5dB -7.4dB -6.0dB 450mV 510mV -9.5dB -7.7dB 480mV -12.0dB RocketIO™ X Transceiver User Guide www.xilinx.com UG035 (v1.5) November 22, 2004 1-800-255-7778...

  • Page 102: Figure 4-12: Output Swing Versus De-Emphasis (%) When Ac Coupled

    Figure 4-12: Output Swing versus De-Emphasis (%) When AC Coupled Vos vs. De-Emphasis (AC Coupled) 0.00 -5.00 -10.00 -15.00 -20.00 De-emphasis (dB) Figure 4-13: Output Swing versus De-Emphasis (dB) When AC Coupled www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778 UG035 (v1.5) November 22, 2004...

  • Page 103: Differential Receiver

    Random Jitter (RJ) RJ is due to stochastic sources, such as substrate, power supply, etc. RJ is additive as the sum of squares, and follows a bell curve. RocketIO™ X Transceiver User Guide www.xilinx.com UG035 (v1.5) November 22, 2004 1-800-255-7778...

  • Page 104: Clock And Data Recovery

    The serial transceiver input is locked to the input data stream through Clock and Data Recovery (CDR), a built-in feature of the RocketIO X transceiver. CDR keys off of the rising and falling edges of incoming data and derives a clock that is representative of the incoming data rate.

  • Page 105: Receive Equalization

    The recovered clock is not guaranteed to be within any tolerance of the local reference and might “wander” in the absence of data and/or transitions. Receive Equalization In addition to transmit emphasis, the RocketIO X transceiver provides a programmable receive equalization feature to further compensate the effects of channel attenuation at high frequencies.

  • Page 106: Figure 4-14: Magnitude (Db) Vs. Frequency (Hz) Plot

    The frequency ranges do not follow LSB to MSB with regard to which frequency range is boosted. Figure 4-14: Magnitude (dB) vs. Frequency (Hz) Plot for all 1024 states of RXFER[9:0] www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778 UG035 (v1.5) November 22, 2004...

  • Page 107: Low Frequency Boosting

    RXFER[3]. Hence, the boost of the transfer function is set at low to high frequencies by the bits RXFER[3:2] = 00, 10, 01 and 11, respectively. ug035_ch4_15b_111003 Figure 4-15: Magnitude (dB) vs. Frequency (Hz) Response for Four Settings of RXFER[3:2] RocketIO™ X Transceiver User Guide www.xilinx.com UG035 (v1.5) November 22, 2004 1-800-255-7778...

  • Page 108: Mid Frequency Boosting

    RXFER[0]. Hence, the boost of the transfer function is set at low to high frequencies by the bits RXFER[1:0] = 00, 01, 10 and 11, respectively. ug035_ch4_16b_111003 Figure 4-16: Magnitude (dB) vs. Frequency (Hz) Response for Four Settings of RXFER[1:0] www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778 UG035 (v1.5) November 22, 2004...

  • Page 109: High Frequency Boosting

    110, 001, 011, 101, and 111, respectively. ug035_ch4_17b_111003 Figure 4-17: Magnitude (dB) vs. Frequency (Hz) Response for Eight Settings of RXFER[6:4] RXFER[9:7] also adjusts a boost in the 500 MHz to 2 GHz range. RocketIO™ X Transceiver User Guide www.xilinx.com UG035 (v1.5) November 22, 2004 1-800-255-7778...

  • Page 110: Figure 4-18: Magnitude (Db) Vs. Frequency (Hz) Response

    RXFER[9:7] are very similar to those curves for RXFER[6:4]. They represent two identical cascaded stages. Changing all six bits results in a cumulative change in the boost frequency. www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778 UG035 (v1.5) November 22, 2004...

  • Page 111: Figure 4-19: Magnitude (Db) Vs. Frequency (Hz) Response

    RXFER[8], RXFER[9], RXFER[7], and RXFER[5], RXFER[6], RXFER[4]. ug035_ch4_19b_111003 Figure 4-19: Magnitude (dB) vs. Frequency (Hz) Response for Eight Settings (out of 64) of RXFER[9:4] RocketIO™ X Transceiver User Guide www.xilinx.com UG035 (v1.5) November 22, 2004 1-800-255-7778...

  • Page 112: Simulation Transmitter Emphasis And Receiver Equalization Settings

    Note: This section uses simulation numbers only. The RocketIO X transceiver incorporates pre-emphasis in the transmitter which preemptively corrects for the PCB loss. In addition, there is an equalizer in the receiver which can post-process the signal to correct for the same loss. Proper transmitter and receiver settings can essentially null the lossy attenuation effects of a PCB completely.

  • Page 113: Table 4-9: Example Signal Paths

    These numbers are based on simulation only, and not based on actual characterization. Therefore, Xilinx emphasizes that these numbers are only estimates (i.e., ballpark numbers); hence, Xilinx is not responsible if these are not the optimum settings for a particular application. More detailed descriptions of the transmit pre-emphasis and receive equalization are given in this chapter, and users are encouraged to read those sections to understand the pre-emphasis and equalization features before trying them out.

  • Page 114: Pcb Design Requirements

    Xilinx, Inc. Power Conditioning Each RocketIO X transceiver has five power supply pins, all of which are sensitive to noise. Table 4-11, summarizes the power supply pins, their names, associated voltages, and estimated power requirements.

  • Page 115: Passive Filtering

    In cases where the RocketIO X transceiver is interfacing with another RocketIO X transceiver, a 1.5V termination voltage is recommended. The LT1963 (LT1963A) circuit’s output capacitors (330 µF and 1 µF) can be placed anywhere on the board, preferably close to the output of the LT1963 device.

  • Page 116: Figure 4-22: Power Filtering Network For One Transceiver

    A/B) and four on the bottom edge (rows AE/AF). Figure 4-23 shows the bottom PCB layer, with lands for the ferrite beads of all supplies: AVCCAUXTX, AVCCAUXRX, VTTX, and www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778 UG035 (v1.5) November 22, 2004...

  • Page 117: High-Speed Serial Trace Design

    High-Speed Serial Trace Design Routing Serial Traces All RocketIO X transceiver I/Os are placed on the periphery of the BGA package to facilitate routing and inspection (since JTAG is not available on serial I/O pins). RocketIO X transceivers have a 50Ω output/input impedance. Controlled impedance traces should be used to connect the RocketIO X transceiver to other compatible transceivers.

  • Page 118: Differential Trace Design

    PCB routes carry noisy signals, such as TTL and other similarly noisy standards. The RocketIO X transceiver is designed to function up to 10.3125 Gb/s through 16 inches of FR4 with two high-bandwidth connectors. Longer trace lengths require use of a low-loss dielectric (for example, Rogers 4350 can essentially double the transmission distance compared to FR4).

  • Page 119: Figure 4-25: Microstrip Edge-Coupled Differential Pair

    0DIFF Dielectric = 4.3 Reference Plane ug035_ch4_21_022703 Figure 4-26: Stripline Edge-Coupled Differential Pair Note: For more information about serial backplane traces, see Appendix E, “Serial Backplane System Design.” RocketIO™ X Transceiver User Guide www.xilinx.com UG035 (v1.5) November 22, 2004 1-800-255-7778...

  • Page 120: Termination

    Chapter 4: Analog Design Considerations Termination The RocketIO X transceiver implements on-chip 50Ω termination in both the transmitter (TXP/TXN) and receiver (RXP/RXN). The output driver and termination are powered by VTTX at 1.5V. This configuration uses a CML approach with 50Ω to TXP and TXN as shown in Figure 4-27.

  • Page 121: Other Important Design Notes

    10.3125 Gb/s when 8B/10B or 64B/66B encoding is used. Different data rates and different encoding schemes may require a different value. DC coupling (direct connection) is preferable in cases where RocketIO X transceivers are interfaced with other RocketIO X transceivers. Passive components are not required when DC coupling is used.

  • Page 122: Reference Clock

    3.3V and not 2.5V (as in the EG2121CA). See Figure 4-32. .1 µF (100 nF) EV-2101CA 100Ω 3.3V-PECL VCSO .1 µF 100Ω 100Ω (100 nF) ug035_ch4_26_111704 Figure 4-32: Reference Clock Oscillator Interface above 400 MHz www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778 UG035 (v1.5) November 22, 2004...

  • Page 123: Chapter 5: Simulation And Implementation

    The period of the clock used is the reference clock divided by two. This clock is connected internally. Refer to for start-up times. RocketIO™ X Transceiver User Guide www.xilinx.com UG035 (v1.5) November 22, 2004 1-800-255-7778...

  • Page 124: Figure 5-1: Pma Initialization

    PMA initialization function relinquishes control of the PMA interface to the fabric PMARXLOCK signal is enabled once the receive PLL locks to data Normal Function ug035_ch3_15_091003 Figure 5-1: PMA Initialization www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778 UG035 (v1.5) November 22, 2004...

  • Page 125: Model Considerations

    HSPICE HSPICE is an analog design model that allows simulation of the RX and TX high-speed transceiver. To obtain these HSPICE models, go to the SPICE Suite Access web page at: http://support.xilinx.com/support/software/spice/spice-request.htm. RocketIO™ X Transceiver User Guide www.xilinx.com UG035 (v1.5) November 22, 2004...

  • Page 126: Mgt Package Pins

    BB29, BB28, BB27, BB26 GT_X3_Y1 A29, A28, A27, A26 GT_X4_Y0 BB25, BB24, BB23, BB22 GT_X4_Y1 A25, A24, A23, A22 GT_X5_Y0 BB21, BB20, BB19, BB18 GT_X5_Y1 A21, A20, A19, A18 www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778 UG035 (v1.5) November 22, 2004...

  • Page 127: Diagnostic Signals

    Pre-driver serial loopback (before the TX output buffer). Same as above, but not including the TX output buffer. The output buffer can be disabled in this loopback mode. RocketIO™ X Transceiver User Guide www.xilinx.com UG035 (v1.5) November 22, 2004 1-800-255-7778...

  • Page 128: Parallel Loopback

    Parallel Loopback In parallel loopback mode, data is looped at the PCS/PMA interface and clocked via the synthesized clock from the RocketIO X transmitter. A stable REFCLK and valid PMA initialization are required. In parallel loopback mode, TXINHIBIT can not be used to suppress the transmit data from being sent onto the TXN/TXP pins, because TXINHIBIT also inhibits the data being looped back to the receiver.

  • Page 129: Appendix A: Rocketio X Transceiver Timing Model

    There are seven clocks associated with the RocketIO X core, but only three of these clocks— RXUSRCL, RXUSRCLK2, and TXUSRCLK2—have I/Os that are synchronous to them. The following table gives a brief description of all of these clocks.

  • Page 130: Appendix A: Rocketio X Transceiver Timing Model

    Table A-1: RocketIO X Clock Descriptions CLOCK SIGNAL DESCRIPTION RXRECCLK Recovered Clock from RocketIO X receiver, locked to incoming data stream. This clock can be scaled (e.g., 64/66) relative to incoming data rate, depending upon the specific operating mode of the receiver.

  • Page 131: Figure A-1: Rocketio X Transceiver Block Diagram

    PMAREGSTROBE PMARXLOCKSEL[1:0] PMARXLOCK REFCLKBSEL RXBLCOKSYNC64B66BUSE RXCOMMADETUSE RXDATAWIDTH[1:0] RXDECC64B66BUSE RXDEC8B10BUSE RXDESCRAM64B66BUSE RXIGNOREBTF RXINTDATAWIDTH[1:0] RXSLIDE TXDATAWIDTH[1:0] TXENC64B66BUSE TXENC8B10BUSE TXGEARBOX64B66BUSE TXINTDATAWIDTH[1:0] TXSCRAM64B66BUSE TXOUTCLK UG035_01_111303 Figure A-1: RocketIO X Transceiver Block Diagram RocketIO™ X Transceiver User Guide www.xilinx.com UG035 (v1.5) November 22, 2004 1-800-255-7778...

  • Page 132: Timing Parameters

    ParameterName _ SIGNAL where ParameterName = T with subscript string defining the timing relationship SIGNAL = name of RocketIO X signal synchronous to the clock ParameterName Format: = Setup time before clock edge G x CK = Hold time after clock edge...

  • Page 133: Timing Diagram And Timing Parameter Tables

    GCKD DATA INPUTS UG012_106_02_100101 Figure A-2: RocketIO X Transceiver Timing Relative to Clock Edge The following four tables list the timing parameters as reported by the implementation tools relative to the clocks given in Table A-1, page 129, along with the RocketIO X signals that are synchronous to each clock.
  • Page 134 Appendix A: RocketIO X Transceiver Timing Model Table A-2: Parameters Relative to RX User Clock (RXUSRCLK) Parameter Function Signals Setup/Hold: _CHBI/T _CHBI Control inputs CHBONDI[4:0] GCCK GCKC Clock to Out: _CHBO Control outputs CHBONDO[4:0] GCKCO Clock: Clock pulse width, High state RXUSRCLK...
  • Page 135 Status outputs TXBUFERR GCKST _TKERR Status outputs TXKERR[7:0] GCKST _TRDIS Data outputs TXRUNDDISP[7:0] GCKDO Clock: Clock pulse width, High state TXUSRCLK2 TX2PWH Clock pulse width, Low state TXUSRCLK2 TX2PWL RocketIO™ X Transceiver User Guide www.xilinx.com UG035 (v1.5) November 22, 2004 1-800-255-7778...
  • Page 136 Clock pulse width, High state TXUSRCLK TXPWH Clock pulse width, Low state TXUSRCLK TXPWL Notes: 1. REFCLK is not synchronous to any RocketIO X signals. 2. TXUSRCLK is not synchronous to any RocketIO X signals. www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778...

  • Page 137: Valid Data And Control Characters

    D16.0 000 10000 011011 0100 100100 1011 D17.0 000 10001 100011 1011 100011 0100 D18.0 000 10010 010011 1011 010011 0100 D19.0 000 10011 110010 1011 110010 0100 RocketIO™ X Transceiver User Guide www.xilinx.com UG035 (v1.5) November 22, 2004 1-800-255-7778...

  • Page 138: Appendix B: 8B/10B Valid Characters

    D16.1 001 10000 011011 1001 100100 1001 D17.1 001 10001 100011 1001 100011 1001 D18.1 001 10010 010011 1001 010011 1001 D19.1 001 10011 110010 1001 110010 1001 www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778 UG035 (v1.5) November 22, 2004...
  • Page 139 D16.2 010 10000 011011 0101 100100 0101 D17.2 010 10001 100011 0101 100011 0101 D18.2 010 10010 010011 0101 010011 0101 D19.2 010 10011 110010 0101 110010 0101 RocketIO™ X Transceiver User Guide www.xilinx.com UG035 (v1.5) November 22, 2004 1-800-255-7778...
  • Page 140 D16.3 011 10000 011011 0011 100100 1100 D17.3 011 10001 100011 1100 100011 0011 D18.3 011 10010 010011 1100 010011 0011 D19.3 011 10011 110010 1100 110010 0011 www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778 UG035 (v1.5) November 22, 2004...
  • Page 141 D16.4 100 10000 011011 0010 100100 1101 D17.4 100 10001 100011 1101 100011 0010 D18.4 100 10010 010011 1101 010011 0010 D19.4 100 10011 110010 1101 110010 0010 RocketIO™ X Transceiver User Guide www.xilinx.com UG035 (v1.5) November 22, 2004 1-800-255-7778...
  • Page 142 D16.5 101 10000 011011 1010 100100 1010 D17.5 101 10001 100011 1010 100011 1010 D18.5 101 10010 010011 1010 010011 1010 D19.5 101 10011 110010 1010 110010 1010 www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778 UG035 (v1.5) November 22, 2004...
  • Page 143 D16.6 110 10000 011011 0110 100100 0110 D17.6 110 10001 100011 0110 100011 0110 D18.6 110 10010 010011 0110 010011 0110 D19.6 110 10011 110010 0110 110010 0110 RocketIO™ X Transceiver User Guide www.xilinx.com UG035 (v1.5) November 22, 2004 1-800-255-7778...
  • Page 144 D16.7 111 10000 011011 0001 100100 1110 D17.7 111 10001 100011 0111 100011 0001 D18.7 111 10010 010011 0111 010011 0001 D19.7 111 10011 110010 1110 110010 0001 www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778 UG035 (v1.5) November 22, 2004...

  • Page 145: Table B-2: Valid Control "K" Characters

    111 11011 110110 1000 001001 0111 K29.7 111 11101 101110 1000 010001 0111 K30.7 111 11110 011110 1000 100001 0111 Notes: 1. Used for testing and characterization only. RocketIO™ X Transceiver User Guide www.xilinx.com UG035 (v1.5) November 22, 2004 1-800-255-7778...
  • Page 146 Appendix B: 8B/10B Valid Characters www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778 UG035 (v1.5) November 22, 2004...

  • Page 147: Appendix C: Pma Attribute Programming Bus

    Appendix C PMA Attribute Programming Bus The RocketIO X transceivers provide a simple, parallel programming bus for dynamically configuring the PMA attribute settings. This gives the end user real-time control of PMA features without the need to use partial reconfiguration or to bring out discrete control ports to the fabric for each and every attribute (not feasible).

  • Page 148: Memory Map

    TXDOWNLEVEL[3:0] 0x06 TXOUTPUTMODE TXANASW TXDIGSW TXEMPHLEVEL[3:0] 0x07 RXDIVRATIOLO RXDIVRATIO[7:0] 0x08 RXDIVRATIOHI SEL_DAC_TRAN[1:0] RXDIVRATIO[13:8] 0x09 RXLOOPFILTER SEL_DAC_FIX[1:0] AFE_FLAT_ RXLOOPFILTERR[2:0] RXLOOPFILTERC[1:0] ENABLE 0x0A RXMODE0 RXREG[1:0] RXVSEL[1:0] RXVCOGAIN RXVCODAC RXCPI RXVCOSW www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778 UG035 (v1.5) November 22, 2004...

  • Page 149: Register Definition

    The defaults for these are primitive dependent, based on reference clock frequency and encoding. Table C-4: TX Clock Multiplier Ratio Definition TXDIVRATIO[3:0] Divider ÷ 4 0000 ÷ 4.125 0001 ÷ 5 0010 0011 Reserved RocketIO™ X Transceiver User Guide www.xilinx.com UG035 (v1.5) November 22, 2004 1-800-255-7778...

  • Page 150: Table C-5: Txclk0 Divider Ratio Definition

    ÷ 4 0000 ÷ 4.125 0001 ÷ 5 0010 0011 Reserved ÷ 8 0100 ÷ 8.25 0101 ÷ 10 0110 0111 Reserved ÷ 16 1000 ÷ 16.5 1001 www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778 UG035 (v1.5) November 22, 2004...

  • Page 151: Txbuswid

    TXLOOPFILTERR[1:0] selects the transmit PLL filter resistor setting. The default is primitive dependent. The loop filter resistor selection is as follows: Table C-9: TXLOOPFILTERR[1:0] Definition TXLOOPFILTERR[1:0] TX Filter Resistor 12 kΩ 6 kΩ RocketIO™ X Transceiver User Guide www.xilinx.com UG035 (v1.5) November 22, 2004 1-800-255-7778...

  • Page 152: Iboost

    DAC mode, the center frequency is controlled by the value of VCODAC[5:0]. The transmit center frequency control is defined as follows: Table C-12: TXVCODAC Definition TXVCODAC TX VCO Center Frequency DAC Controlled Automatic (Default) www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778 UG035 (v1.5) November 22, 2004...

  • Page 153: Txvcogain

    45 mA 60 mA TXDOWNLEVEL[3:0] TXDOWNLEVEL[3:0] selects the transmit line driver current (and, thus, output voltage swing). The output swing is defined in the RocketIO X Transceiver User Guide. RocketIO™ X Transceiver User Guide www.xilinx.com UG035 (v1.5) November 22, 2004...

  • Page 154: Prdrvoff

    Slew Rate Fast Slow TXEMPHLEVEL[3:0] TXEMPHLEVEL[3:0] selects the transmit line driver emphasis current level (and, thus, emphasis voltage level). The emphasis levels are defined in the RocketIO X Transceiver User Guide. www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778 UG035 (v1.5) November 22, 2004...

  • Page 155: Txdigsw

    0001 ÷ 10 0010 0011 Reserved ÷ 16 0100 ÷ 16.5 0101 ÷ 20 0110 0111 Reserved ÷ 32 1000 ÷ 33 1001 ÷ 40 1010 1011 Reserved RocketIO™ X Transceiver User Guide www.xilinx.com UG035 (v1.5) November 22, 2004 1-800-255-7778...

  • Page 156: Table C-22: Rxclk0 Divider Ratio Definition

    Table C-23: RXRECCLK Divider Ratio Definition RXDIVRATIO[7:4] Divider ÷ 4 0000 ÷ 4.125 0001 ÷ 5 0010 0011 Reserved ÷ 8 0100 ÷ 8.25 0101 ÷ 10 0110 www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778 UG035 (v1.5) November 22, 2004...

  • Page 157: Rxloopfilterc[1:0]

    RXLOOPFILTERC[1:0] selects the receiver PLL filter capacitor setting. The default is primitive dependent. The receiver loop filter capacitor selection is as follows: Table C-26: RXLOOPFILTERC[1:0] Definition RXLOOPFILTERC[1:0] RX Filter Capacitor 15 pF 30 pF 30 pF 45 pF RocketIO™ X Transceiver User Guide www.xilinx.com UG035 (v1.5) November 22, 2004 1-800-255-7778...

  • Page 158: Rxloopfilterr[2:0]

    300 µA 600 µA RXVCODAC RXVCODAC selects between automatic and DAC control of receiver VCO center frequency. The default is 0 (Automatic, i.e., independent of VCODAC[5:0]). When set to www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778 UG035 (v1.5) November 22, 2004...

  • Page 159: Rxvcogain

    RXREG[1:0] sets the receiver VCO regulator output current. The default is primitive dependent. The receiver regulator current is defined as follows: Table C-33: RXREG[1:0] Definition RXREG[1:0] RX Regulator Current 13 mA 27 mA 40 mA 53 mA RocketIO™ X Transceiver User Guide www.xilinx.com UG035 (v1.5) November 22, 2004 1-800-255-7778...

  • Page 160: Rxvselcp[1:0]

    The receiver charge pump common mode voltage is defined as fol- lows: Table C-34: RXVSELCP[1:0] Definition RXVSELCP[1:0] RX Charge Pump Common Mode 600 mV 720 mV 840 mV 960 mV www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778 UG035 (v1.5) November 22, 2004...

  • Page 161: Rxcpgain

    RXFEI[1:0] sets the receiver front end/equalizer current. The default is 11 (24 mA). The receiver front-end current is defined as follows: Table C-37: RXFEI[1:0] Definition RXFEI[1:0] RX Front End Current 6 mA 12 mA 18 mA 24 mA (Default) RocketIO™ X Transceiver User Guide www.xilinx.com UG035 (v1.5) November 22, 2004 1-800-255-7778...

  • Page 162: Rxfer[9:0]

    For details, see “Receive Equalization” in Chapter 4 in the RocketIO X Transceiver User Guide. RXFLCPI[1:0] RXFLCPI[1:0] sets the fine loop charge pump current. The default is 00 (40 µA). The receiver fine loop charge pump current is defined as follows:...

  • Page 163: Txdigen

    RXEN enables and disables receiver operation. The default is 1 (Enabled). For proper operation, the bias must also be enabled. The receiver control is defined as follows: Table C-44: RXEN Definition RXEN RX Operation Disabled Enabled (Default) RocketIO™ X Transceiver User Guide www.xilinx.com UG035 (v1.5) November 22, 2004 1-800-255-7778...

  • Page 164: Txdrven

    This section describes the programmability of the fine loop charge pump (CP) to achieve offset adjustment that is data-density independent. The fine loop CP is made of a Phase CP, Transition CP, and DC current sources as shown in Figure C-2. www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778 UG035 (v1.5) November 22, 2004...

  • Page 165: Figure C-2: Fine Loop Charge Pump

    The default code for DC_CP current is 0 and for the Tran_CP code is 0. This will set the two currents to their nominal values. DC_CP bus is accessed through SEL_DAC_FIX [3:0] RocketIO™ X Transceiver User Guide www.xilinx.com UG035 (v1.5) November 22, 2004 1-800-255-7778...

  • Page 166: Figure C-3: Sampling Point Offset

    Table C-47. For example, a code of (1, 1) can be used. This code causes the TRAN_CP current and the DC_CP current to be 12.5% higher than the nominal value, which will www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778 UG035 (v1.5) November 22, 2004...
  • Page 167 Data-Density Independent Phase Adjustment for CDR cause an offset in the sampling point. However, this offset is data-density dependent and can eventually result in a loss of lock. RocketIO™ X Transceiver User Guide www.xilinx.com UG035 (v1.5) November 22, 2004 1-800-255-7778...
  • Page 168 Appendix C: PMA Attribute Programming Bus www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778 UG035 (v1.5) November 22, 2004...

  • Page 169: Introduction

    BREFCLK As with Virtex-II Pro FPGAs, at speeds of 2.5 Gb/s or greater, the REFCLK configuration introduces more than the maximum allowable jitter to the RocketIO X transceiver. For this reason, the BREFCLK configuration is required. The BREFCLK configuration uses dedicated routing resources that reduce jitter. BREFCLK...

  • Page 170: Figure D-1: Refclk/Brefclk Selection Logic

    BREFCLK frequencies (up to 645 MHz). For more information, see the reference clock sections of this guide and the RocketIO Transceiver User Guide ( UG024 www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778 UG035 (v1.5) November 22, 2004...

  • Page 171: Power Regulation And Filtering

    (relative to Virtex-II Pro), including their names, associated voltages, and power requirements. To operate properly, RocketIO and RocketIO X transceivers require a certain level of noise isolation from surrounding noise sources. For this reason, it is required that both dedicated voltage regulators and passive high-frequency filtering be used to power RocketIO and RocketIO X circuitry.

  • Page 172: High-Speed Serial I/O Termination

    1.8-2.5V. For DC coupling of two Virtex-II Pro X devices, a 1.5V CML termination for VTRX is recommended. VTRX 50Ω 50Ω x700_04_022103 Figure D-4: Receive Termination www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778 UG035 (v1.5) November 22, 2004...

  • Page 173: Migration Differences

    Port Widths and Byte Mapping All ports that are byte mapped are 8 bits wide instead of 4 bits wide as in RocketIO X transceivers to support up to 8 bytes or eight 10-bit words at the data interface. The mapping is the same.

  • Page 174: Channel Bonding

    Table 1-4, page The CHANNEL_BOND_WAIT and CHANNEL_BOND_OFFSET are gone. For the RocketIO X transceiver, they are derived from CHANNEL_BOND_LIMIT, which should be set to 16. CHAN_BOND_SEQ_*_MASK has been added. It is a 4-bit signal that allows the user to mask out any part of the channel bonding sequence (make it a don’t care) by setting any bit of the mask to 1 (all zeros only bond on the exact sequence;...

  • Page 175: 8B/10B

    PMARXLOCK - This port indicates that the RX PLL has locked in the fine loop. Serialization In the RocketIO transceiver, the most significant byte is sent first; in the RocketIO X transceiver, the least significant byte is sent first. Within a byte, the bits are still sent in the same order, i.e., bit 9 is sent first and bit 0 is sent last.
  • Page 176 Appendix D: Virtex-II Pro to Virtex-II Pro X FPGA Design Migration www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778 UG035 (v1.5) November 22, 2004...

  • Page 177: Appendix E: Serial Backplane System Design

    Appendix E Serial Backplane System Design Additional PCB design guidelines are required to meet the demands of the RocketIO X transceiver for operation above 3.125 Gb/s. Backplane system design guidelines can be divided into three separate components. One component is directed toward the launch from the package onto the line card or switch card PCB.

  • Page 178: Figure E-1: Backdrilling Process

    A second PCB is then attached to the first to complete the backplane, effectively moving the signal layer from the bottom layer www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778 UG035 (v1.5) November 22, 2004...

  • Page 179: Package To Pcb Launch

    50 mil. Rectangular antipads should be utilized in a similar fashion as discussed in the previous section. Finally, pads should be removed from all unused signal layers. RocketIO™ X Transceiver User Guide www.xilinx.com UG035 (v1.5) November 22, 2004 1-800-255-7778...
  • Page 180 Appendix E: Serial Backplane System Design www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778 UG035 (v1.5) November 22, 2004...

  • Page 181: Appendix F: Modifiable Attributes

    4'b0000, 4-bit binary CHAN_BOND_SEQ_2_USE FALSE, TRUE CHAN_BOND_SEQ_LEN 1, 1, 2, 3, 4, 8 CLK_COR_8B10B_DE FALSE, TRUE CLK_COR_ADJ_MAX UNUSED CLK_COR_INSERT_IDLE_FLAG UNUSED CLK_COR_KEEP_IDLE UNUSED CLK_COR_MAX_LAT 36, 0…63 CLK_COR_MIN_LAT 28, 0…63 CLK_COR_REPEAT_WAIT UNUSED RocketIO™ X Transceiver User Guide www.xilinx.com UG035 (v1.5) November 22, 2004 1-800-255-7778...

  • Page 182: Appendix F: Modifiable Attributes

    25_40, 28_10, 28_20, 28_40, 31_16, 31_32, 31_8 RX_BUFFER_USE TRUE, FALSE RX_LOS_INVALID_INCR 1, 2, 4, 8, 16, 32, 64, 128 RX_LOS_THRESHOLD 4, 8, 16, 32, 64, 128, 256, 512 RX_LOSS_OF_SYNC_FSM TRUE, FALSE SH_CNT_MAX 64, 1…255 www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778 UG035 (v1.5) November 22, 2004...

  • Page 183: Table F-2: Default Attribute Values: Gt10_Aurora_1, Gt10_Aurora_2

    UNUSED CLK_COR_INSERT_IDLE_FLAG FALSE FALSE FALSE CLK_COR_KEEP_IDLE FALSE FALSE FALSE CLK_COR_MAX_LAT 36, 0…63 36, 0…63 36, 0…63 CLK_COR_MIN_LAT 28, 0…63 28, 0…63 28, 0…63 CLK_COR_REPEAT_WAIT CLK_COR_SEQ_1_1 11'b00111110111 11'b00111110111 11'b00111110111 RocketIO™ X Transceiver User Guide www.xilinx.com UG035 (v1.5) November 22, 2004 1-800-255-7778...

  • Page 184: Appendix F: Modifiable Attributes

    25_10 25_20 25_40 RX_BUFFER_USE TRUE TRUE TRUE RX_LOS_INVALID_INCR RX_LOS_THRESHOLD RX_LOSS_OF_SYNC_FSM FALSE FALSE FALSE SH_CNT_MAX UNUSED UNUSED UNUSED SH_INVALID_CNT_MAX UNUSED UNUSED UNUSED TX_BUFFER_USE TRUE, FALSE TRUE, FALSE TRUE, FALSE www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778 UG035 (v1.5) November 22, 2004...

  • Page 185: Table F-3: Default Attribute Values: Gt10_Aurorax_4, Gt10_Aurorax_8

    CLK_COR_8B10B_DE UNUSED CLK_COR_ADJ_MAX UNUSED CLK_COR_INSERT_IDLE_FLAG UNUSED CLK_COR_KEEP_IDLE UNUSED CLK_COR_MAX_LAT 36, 0…63 CLK_COR_MIN_LAT 28, 0…63 CLK_COR_REPEAT_WAIT UNUSED CLK_COR_SEQ_1_1 11'b10000011110 CLK_COR_SEQ_1_2 11'b00000000000 CLK_COR_SEQ_1_3 11'b00000000000 CLK_COR_SEQ_1_4 11'b00000000000 CLK_COR_SEQ_1_MASK 4'b0000, 4-bit binary RocketIO™ X Transceiver User Guide www.xilinx.com UG035 (v1.5) November 22, 2004 1-800-255-7778...

  • Page 186: Appendix F: Modifiable Attributes

    1, 2, 4, 8, 16, 32, 64, 128 RX_LOS_THRESHOLD 4, 8, 16, 32, 64, 128, 256, 512 RX_LOSS_OF_SYNC_FSM TRUE, FALSE SH_CNT_MAX 64, 1…255 SH_INVALID_CNT_MAX 16, 1…255 TX_BUFFER_USE TRUE, FALSE www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778 UG035 (v1.5) November 22, 2004...

  • Page 187: Table F-4: Default Attribute Values: Gt10_10Ge_8, Gt10_10Gfc_4

    UNUSED UNUSED CLK_COR_SEQ_1_1 11'b10000011110 11'b10000011110 11'b10000011110 CLK_COR_SEQ_1_2 11'b00000000000 11'b00000000000 11'b00000000000 CLK_COR_SEQ_1_3 11'b00000000000 11'b00000000000 11'b00000000000 CLK_COR_SEQ_1_4 11'b00000000000 11'b00000000000 11'b00000000000 CLK_COR_SEQ_1_MASK 4'b0000, 4-bit binary 4'b0000, 4-bit binary 4'b0000, 4-bit binary RocketIO™ X Transceiver User Guide www.xilinx.com UG035 (v1.5) November 22, 2004 1-800-255-7778...

  • Page 188: Appendix F: Modifiable Attributes

    RX_LOSS_OF_SYNC_FSM TRUE, FALSE TRUE, FALSE TRUE, FALSE SH_CNT_MAX 64, 1…255 64, 1…255 64, 1…255 SH_INVALID_CNT_MAX 16, 1…255 16, 1…255 16, 1…255 TX_BUFFER_USE TRUE, FALSE TRUE, FALSE TRUE, FALSE www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778 UG035 (v1.5) November 22, 2004...

  • Page 189: Table F-5: Default Attribute Values: Gt10_Pci_Express_1, Gt10_Pci_Express_2

    UNUSED UNUSED CLK_COR_SEQ_1_1 11'b00100011100 11'b00100011100 11'b00100011100 CLK_COR_SEQ_1_2 11'b00000000000 11'b00000000000 11'b00000000000 CLK_COR_SEQ_1_3 11'b00000000000 11'b00000000000 11'b00000000000 CLK_COR_SEQ_1_4 11'b00000000000 11'b00000000000 11'b00000000000 CLK_COR_SEQ_1_MASK 4'b0000, 4-bit binary 4'b0000, 4-bit binary 4'b0000, 4-bit binary RocketIO™ X Transceiver User Guide www.xilinx.com UG035 (v1.5) November 22, 2004 1-800-255-7778...

  • Page 190: Appendix F: Modifiable Attributes

    4, 8, 16, 32, 64, 128, 256, 512 RX_LOSS_OF_SYNC_FSM TRUE, FALSE TRUE, FALSE TRUE, FALSE SH_CNT_MAX UNUSED UNUSED UNUSED SH_INVALID_CNT_MAX UNUSED UNUSED UNUSED TX_BUFFER_USE TRUE, FALSE TRUE, FALSE TRUE, FALSE www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778 UG035 (v1.5) November 22, 2004...

  • Page 191: Table F-6: Default Attribute Values: Gt10_Infiniband_1, Gt10_Infiniband_2

    11'b00100011100 11'b00100011100 CLK_COR_SEQ_1_2 11'b00000000000 11'b00000000000 11'b00000000000 CLK_COR_SEQ_1_3 11'b00000000000 11'b00000000000 11'b00000000000 CLK_COR_SEQ_1_4 11'b00000000000 11'b00000000000 11'b00000000000 CLK_COR_SEQ_1_MASK 4'b0000, 4-bit binary 4'b0000, 4-bit binary 4'b0000, 4-bit binary CLK_COR_SEQ_2_1 11'b00000000000 11'b00000000000 11'b00000000000 RocketIO™ X Transceiver User Guide www.xilinx.com UG035 (v1.5) November 22, 2004 1-800-255-7778...

  • Page 192: Appendix F: Modifiable Attributes

    4, 8, 16, 32, 64, 128, 256, 512 RX_LOSS_OF_SYNC_FSM TRUE, FALSE TRUE, FALSE TRUE, FALSE SH_CNT_MAX UNUSED UNUSED UNUSED SH_INVALID_CNT_MAX UNUSED UNUSED UNUSED TX_BUFFER_USE TRUE, FALSE TRUE, FALSE TRUE, FALSE www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778 UG035 (v1.5) November 22, 2004...

  • Page 193: Table F-7: Default Attribute Values: Gt10_Xaui_1, Gt10_Xaui_2

    UNUSED UNUSED CLK_COR_SEQ_1_1 11'b00100011100 11'b00100011100 11'b00100011100 CLK_COR_SEQ_1_2 11'b00000000000 11'b00000000000 11'b00000000000 CLK_COR_SEQ_1_3 11'b00000000000 11'b00000000000 11'b00000000000 CLK_COR_SEQ_1_4 11'b00000000000 11'b00000000000 11'b00000000000 CLK_COR_SEQ_1_MASK 4'b0000, 4-bit binary 4'b0000, 4-bit binary 4'b0000, 4-bit binary RocketIO™ X Transceiver User Guide www.xilinx.com UG035 (v1.5) November 22, 2004 1-800-255-7778...

  • Page 194: Appendix F: Modifiable Attributes

    4, 8, 16, 32, 64, 128, 256, 512 RX_LOSS_OF_SYNC_FSM TRUE, FALSE TRUE, FALSE TRUE, FALSE SH_CNT_MAX UNUSED UNUSED UNUSED SH_INVALID_CNT_MAX UNUSED UNUSED UNUSED TX_BUFFER_USE TRUE, FALSE TRUE, FALSE TRUE, FALSE www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778 UG035 (v1.5) November 22, 2004...

  • Page 195: Table F-8: Default Attribute Values: Gt10_Oc192_4 And Gt10_Oc192_8

    UNUSED CLK_COR_MIN_LAT UNUSED UNUSED CLK_COR_REPEAT_WAIT UNUSED UNUSED CLK_COR_SEQ_1_1 UNUSED UNUSED CLK_COR_SEQ_1_2 UNUSED UNUSED CLK_COR_SEQ_1_3 UNUSED UNUSED CLK_COR_SEQ_1_4 UNUSED UNUSED CLK_COR_SEQ_1_MASK UNUSED UNUSED CLK_COR_SEQ_2_1 UNUSED UNUSED CLK_COR_SEQ_2_2 UNUSED UNUSED RocketIO™ X Transceiver User Guide www.xilinx.com UG035 (v1.5) November 22, 2004 1-800-255-7778...

  • Page 196: Appendix F: Modifiable Attributes

    4, 8, 16, 32, 64, 128, 256, 512 4, 8, 16, 32, 64, 128, 256, 512 RX_LOSS_OF_SYNC_FSM TRUE, FALSE TRUE, FALSE SH_CNT_MAX UNUSED UNUSED SH_INVALID_CNT_MAX UNUSED UNUSED TX_BUFFER_USE TRUE, FALSE TRUE, FALSE www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778 UG035 (v1.5) November 22, 2004...
  • Page 197 CLK_COR_SEQ_1_1 UNUSED UNUSED UNUSED CLK_COR_SEQ_1_2 UNUSED UNUSED UNUSED CLK_COR_SEQ_1_3 UNUSED UNUSED UNUSED CLK_COR_SEQ_1_4 UNUSED UNUSED UNUSED CLK_COR_SEQ_1_MASK UNUSED UNUSED UNUSED CLK_COR_SEQ_2_1 UNUSED UNUSED UNUSED CLK_COR_SEQ_2_2 UNUSED UNUSED UNUSED RocketIO™ X Transceiver User Guide www.xilinx.com UG035 (v1.5) November 22, 2004 1-800-255-7778...

  • Page 198: Appendix F: Modifiable Attributes

    4, 8, 16, 32, 64, 128, 256, 512 RX_LOSS_OF_SYNC_FSM TRUE, FALSE TRUE, FALSE TRUE, FALSE SH_CNT_MAX UNUSED UNUSED UNUSED SH_INVALID_CNT_MAX UNUSED UNUSED UNUSED TX_BUFFER_USE TRUE, FALSE TRUE, FALSE TRUE, FALSE www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778 UG035 (v1.5) November 22, 2004...

  • Page 199: Appendix G: Related Online Documents

    (PRBS) pattern, a clock pattern, or a user-defined pattern. The reference design provides access to the PMA attribute programming bus on the RocketIO X MGT, which enables real-time control of PMA features, such as the TX output swing, TX pre-emphasis, and RX equalization. The reference design utilizes the UltraController™...

  • Page 200: Characterization Reports

    RPT007: RocketIO™ Transceiver Characterization Report for the Virtex-II Pro X FPGAs This report discusses the performance of the RocketIO Transceiver for the Virtex-II Pro X FPGAs. To access this report, go to: http://www.xilinx.com/software/spice/spice-request.htm White Papers www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778 UG035 (v1.5) November 22, 2004...

  • Page 201: Index

    Backdrilled vs Non-Backdrilled Channel Analog Design Considerations Characteristics (figure) Summary Architecture Wizard, to create HDL code Backdrilling Process (figure) Symbol Detection Block Diagram, RocketIO X Transceiver Communications Standards Supported Attribute (defined) by RocketIO X Transceiver (table) Attributes Block Format Function Control Codes...
  • Page 202 Interface Description Channel Bonding Package to PCB Launch PMA Attribute Programming Bus Clock Correction Parameters Relative to Clocking and Data Width RX User Clock (RXUSRCLK) (table) Comma Alignment www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778 UG035 (v1.5) November 22, 2004...
  • Page 203 Clock Descriptions (table) RXRECCLK Bus Ports (table) Cores per Device Type (table) RXRESET Bus Waveform (figure) Features RXRUNDISP Programming Bus RocketIO X Transceiver RXSLIDE PMA Clock Parameters (table) Basic Architecture and Capabilities RXUSRCLK PMA Initialization RXUSRCLK2 Block Diagram PMARXLOCKSEL TXBUFERR...
  • Page 204 User Guide Organization Valid Data and Control Characters, 8B/10B Valid Data Characters Virtex-II Pro X BREFCLK Pin Numbers Vitesse Disparity Example Voltage Changes for Virtex-II Pro X FPGA Power Regulation www.xilinx.com RocketIO™ X Transceiver User Guide 1-800-255-7778 UG035 (v1.5) November 22, 2004...

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