Xilinx 7 Series User Manual page 97

Table 3-15: TX Buffer Bypass Ports (Cont'd)
Port Dir
TXPHINITDONE Out
TXDLYSRESETDONE Out
TXSYNCMODE In
TXSYNCALLIN In
TXSYNCIN In
TXSYNCOUT Out
TXSYNCDONE Out
Table 3-16: TX Buffer Attributes
Attribute
TXBUF_EN
TX_XCLK_SEL
TXPH_CFG
TXPH_MONITOR_SEL
TXPHDLY_CFG
TXDLY_CFG
TXDLY_LCFG
TXDLY_TAP_CFG
TXSYNC_MULTILANE
TXSYNC_SKIP_DA
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
Clock Domain
Async Indicates that TX phase alignment initialization is done.
Async Indicates that TX delay alignment soft reset is done.
Async Reserved. Tie to GND.
Async Reserved. Tie to GND.
Async Reserved. Tie to GND.
Async Reserved.
Async Reserved.
Type
String Use or bypass the TX buffer.
TRUE: Uses the TX buffer (default).
FALSE: Bypasses the TX buffer (advanced feature).
String Selects the clock source used to drive the PMA parallel clock domain (XCLK).
TXOUT: Selects TXOUTCLK as the source of XCLK. Used when using the
TX buffer.
TXUSR: Selects TXUSRCLK as the source of XCLK. Used when bypassing the
TX buffer.
16-bit Binary Reserved. The recommended value from the 7 Series FPGAs Transceivers Wizard
should be used.
5-bit Binary Reserved. The recommended value from the 7 Series FPGAs Transceivers Wizard
should be used.
24-bit Binary TX phase and delay alignment configuration.
TXPHDLY_CFG[19] = 1 is used to set the TX delay alignment tap to the full range
of ±4 ns.
TXPHDLY_CFG[19] = 0 is used to set the TX delay alignment tap to the half range
of ±2 ns.
Reserved. The recommended value from the 7 Series FPGAs Transceivers Wizard
should be used.
16-bit Binary Reserved. The recommended value from the 7 Series FPGAs Transceivers Wizard
should be used.
9-bit Binary Reserved. The recommended value from the 7 Series FPGAs Transceivers Wizard
should be used.
16-bit Binary Reserved. The recommended value from the 7 Series FPGAs Transceivers Wizard
should be used.
1-bit Binary Reserved. Tie to 1'b0.
1-bit Binary Reserved. Tie to 1'b0.
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TX Buffer Bypass
Description
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