Xilinx 7 Series User Manual page 290

Appendix D: DRP Address Map of the GTP Transceiver
Table D-2: DRP Map of GTPE2_CHANNEL Primitive (Cont'd)
DRP
DRP Bits
Address
6
0041
5
0041
4
0041
3:0
0041
14
0044
13:10
0044
9:0
0044
15:10
0045
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R/W Attribute Name
R/W ALIGN_MCOMMA_DET
R/W SHOW_REALIGN_COMMA
R/W ALIGN_COMMA_DOUBLE
R/W RXSLIDE_AUTO_WAIT
R/W CLK_CORRECT_USE
R/W CLK_COR_SEQ_1_ENABLE
R/W CLK_COR_SEQ_1_1
R/W CLK_COR_MAX_LAT
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Attribute Attribute
Bits Encoding
FALSE
0
TRUE
FALSE
0
TRUE
FALSE
0
TRUE
0
1
2
3
4
5
6
7
3:0
8
9
10
11
12
13
14
15
FALSE
0
TRUE
3:0 0-15
9:0 0-1023
6
5:0 7
8
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
DRP
Encoding
0
1
0
1
0
1
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
1
0-15
0-1023
6
7
8