Xilinx 7 Series User Manual page 45

X-Ref Target - Figure 2-15
TXRESETDONE
TX RESET FSM
GTP Transceiver TX Component Reset
TX PMA and TX PCS can be reset individually. GTTXRESET must be driven constantly Low
during the TXPMARESET or TXPCSRESET process before finish.
Driving TXPMARESET from High to Low starts the PMA reset process. TXPCSRESET must be
driven constantly Low during the TXPMARESET process. In sequential mode
reset state machine automatically starts the PCS reset after finishing the PMA reset, if
TXUSERRDY is High.
X-Ref Target - Figure 2-16
TXRESETDONE
TX RESET FSM
Driving TXPCSRESET from High to Low starts the PCS reset process when TXUSERRDY is
High. TXPMARESET must be driven constantly Low when the PCS is in reset process. In
sequential mode, the reset state machine only resets the PCS (see
X-Ref Target - Figure 2-17
TXRESETDONE
TX RESET FSM
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
GTTXRESET
TXUSERRDY
IDLE
Figure 2-15: GTP Transceiver Transmitter Reset after GTTXRESET Pulse
TXPMARESET
TXUSERRDY
IDLE
Figure 2-16: TXPMARESET in Sequential Mode
TXPCSRESET
TXUSERRDY
IDLE
Figure 2-17: TXPCSRESET in Sequential Mode
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WAIT TXPMARESET
TXPMARESET_TIME
WAIT TXPMARESET
TXPMARESET_TIME
WAIT TXPCSRESET
TXPCSRESET_TIME
Reset and Initialization
TXPCSRESET IDLE
TXPCSRESET_TIME
UG482_c2_115_020713
(Figure 2-16), the
TXPCSRESET IDLE
TXPCSRESET_TIME
UG482_c2_116_020713
Figure 2-17).
IDLE
UG482_c2_116_020713
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