Xilinx 7 Series User Manual page 280

Appendix D: DRP Address Map of the GTP Transceiver
Table D-2: DRP Map of GTPE2_CHANNEL Primitive (Cont'd)
DRP
DRP Bits
Address
0015
12:6
(Cont'd)
5:0
0015
280
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R/W Attribute Name
R/W SAS_MAX_COM
R/W SATA_MAX_BURST
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Attribute Attribute
Bits Encoding
99
100
101
102
103
104
105
106
107
108
109
110
111
112
6:0 113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
1
5:0 2
3
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
DRP
Encoding
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
1
2
3