Xilinx 7 Series User Manual page 118

Chapter 3: Transmitter
Table 3-28: TX Configurable Driver Ports (Cont'd)
Port
TXPRECURSOR[4:0]
TXPRECURSORINV
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Dir Clock Domain
In Async Transmitter pre-cursor TX pre-emphasis control. The default is user
specified. All listed values (dB) are typical.
5'b00000
5'b00001
5'b00010
5'b00011
5'b00100
5'b00101
5'b00110
5'b00111
5'b01000
5'b01001
5'b01010
5'b01011
5'b01100
5'b01101
5'b01110
5'b01111
5'b10000
5'b10001
5'b10010
5'b10011
5'b10100
5'b10101
5'b10110
5'b10111
5'b11000
5'b11001
5'b11010
5'b11011
5'b11100
5'b11101
5'b11110
5'b11111
In Async When set to 1'b1, inverts the polarity of the TXPRECURSOR coefficient.
The default is 1'b0.
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Description
[4:0] Emphasis (dB)
0.00
0.22
0.45
0.68
0.92
1.16
1.41
1.67
1.94
2.21
2.50
2.79
3.10
3.41
3.74
4.08
4.44
4.81
5.19
5.60
6.02
6.02
6.02
6.02
6.02
6.02
6.02
6.02
6.02
6.02
6.02
6.02
7 Series FPGAs GTP Transceivers User Guide
Coefficient Units
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
20
20
20
20
20
20
20
20
20
20
20
UG482 (v1.9) December 19, 2016