Xilinx 7 Series User Manual page 289

Table D-2: DRP Map of GTPE2_CHANNEL Primitive (Cont'd)
DRP
DRP Bits
Address
0041
12:8
(Cont'd)
7
0041
7 Series FPGAs GTP Transceivers User Guide
UG482 (v1.9) December 19, 2016
R/W Attribute Name
R/W RX_SIG_VALID_DLY
R/W ALIGN_PCOMMA_DET
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Attribute Attribute
Bits Encoding
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
4:0
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
FALSE
0
TRUE
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DRP
Encoding
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
1
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